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參數(shù)資料
| 型號： | MCM63P733ATQ133R |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | ER 5C 5#16S PIN RECP |
| 中文描述： | 128K X 32 CACHE SRAM, 4 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 238K |
| 代理商： | MCM63P733ATQ133R |
MCM63P733A
8
MOTOROLA FAST SRAM
SUPPLY CURRENTS
Parameter
Symbol
Min
Typ
Max
±
1
Unit
μ
A
Notes
Input Leakage Current (0 V
≤
Vin
≤
VDD)
Output Leakage Current (0 V
≤
Vin
≤
VDDQ)
AC Supply Current (Device Selected,
All Outputs Open, Freq = Max)
Includes VDD Only
Ilkg(I)
Ilkg(O)
IDDA
—
—
1, 2
—
—
±
1
μ
A
MCM63P733A–133
MCM63P733A–117
MCM63P733A–100
MCM63P733A–90
—
—
TBD
mA
3, 4, 5
CMOS Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, All Inputs Static at CMOS Levels)
Sleep Mode Supply Current (Sleep Mode, Freq = Max,
VDD = Max, All Other Inputs Static at CMOS Levels,
ZZ
≥
VDD – 0.2 V)
TTL Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, All Inputs Static at TTL Levels)
Clock Running (Device Deselected,
Freq = Max, VDD = Max, All Inputs
Toggling at CMOS Levels)
ISB2
—
—
TBD
mA
6, 8
IZZ
—
—
2
mA
2, 7, 8
ISB3
—
—
TBD
mA
6, 9
MCM63P733A–133
MCM63P733A–117
MCM63P733A–100
MCM63P733A–90
ISB4
—
—
TBD
mA
3, 4,
5, 6, 8
Static Clock Running (Device Deselected, MCM63P733A–133
Freq = Max, VDD = Max, All Inputs
Static at TTL Levels)
MCM63P733A–117
MCM63P733A–100
MCM63P733A–90
ISB5
—
—
TBD
mA
6, 9
NOTES:
1. LBO pin has an internal pullup and will exhibit leakage currents of
±
5
μ
A.
2. ZZ pin has an internal pulldown and will exhibit leakage currents of
±
5
μ
A.
3. Reference AC Operating Conditions and Characteristics for input and timing.
4. All addresses transition simultaneously low (LSB) then high (MSB).
5. Data states are all zero.
6. Device is deselected as defined by the Truth Table.
7. Device in Sleep Mode as defined by the Asynchronous Truth Table.
8. CMOS levels for I/O’s are VIT
≤
VSS + 0.2 V or
≥
VDDQ – 0.2 V. CMOS levels for other inputs are Vin
≤
VSS + 0.2 V or
≥
VDD – 0.2 V.
9. TTL levels for I/O’s are VIT
≤
VIL or
≥
VIH2. TTL levels for other inputs are Vin
≤
VIL or
≥
VIH.
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70
°
C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Min
Typ
Max
Unit
Input Capacitance
Cin
CI/O
—
4
5
pF
Input/Output Capacitance
—
7
8
pF
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