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參數(shù)資料
| 型號(hào)： | MCM64PC32T |
| 廠商： | Motorola, Inc. |
| 英文描述： | 256K/512K Pipelined BurstRAM Secondary Cache Module for Pentium |
| 中文描述： | 256K/512K流水線BurstRAM二級(jí)高速緩存模塊奔騰 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 167K |
| 代理商： | MCM64PC32T |
MCM64PC32T
MCM64PC64T
13
MOTOROLA FAST SRAM
TAG RAM WRITE CYCLE
(See Notes 1 and 2)
– 15
Parameter
Symbol
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
tAVWL
tAVWH
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
15
—
ns
3
Address Setup Time
0
—
ns
Address Valid to End of Write
12
—
ns
Data Valid to End of Write
7
—
ns
Data Hold Time
0
—
ns
Write Low to Output High–Z
0
7
ns
5,6,7
Write High to Output Active
4
—
ns
5,6,7
Write Recovery Time
0
—
ns
NOTES:
1. A write occurs when CWE is low.
2. If CG goes low coincident with or after CWE goes low, the output will remain in a high impedance state.
3. All timings are referenced from the last valid address to the first address transition.
4. If CG
≥
VIH, the output will remain in a high impedance state.
5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device.
6. Transition is measured
±
500 mV from steady–state voltage with load of Figure 3b.
7. This parameter is sampled and not 100% tested.
TAG RAM WRITE CYCLE
(See Notes 1 and 2)
DATA VALID
tDVWH
tAVWL
tAVWH
tAVAV
tWHAX
tWLWH
tWHDX
tWLQZ
tWHQX
HIGH Z
HIGH Z
AX (ADDRESS)
TWE
Q (DATA OUT)
D (DATA IN)
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