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參數資料
| 型號： | MCM69C433 |
| 廠商： | Motorola, Inc. |
| 英文描述： | A Flexible Content-Addressable Memory (16K x 64 CAM)(1M內容可定址存儲器) |
| 中文描述： | 一個靈活的內容尋址存儲器（16K的× 64 CAM）的（100萬內容可定址存儲器） |
| 文件頁數： | 19/22頁 |
| 文件大小： | 167K |
| 代理商： | MCM69C433 |
MCM69C433
SCM69C433
19
MOTOROLA FAST SRAM
TEST ACCESS PORT PINS
TCK — TEST CLOCK (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TMS — TEST MODE SELECT (INPUT)
The TMS input is sampled on the rising edge of TCK. This
is the command input for the TAP controller state machine.
An undriven TMS input will produce the same result as a
logic 1 input level.
TDI — TEST DATA IN (INPUT)
The TDI input is sampled on the rising edge of TCK. This is
the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is deter-
mined by the state of the TAP controller state machine and
the instruction that is currently loaded in the TAP instruction
register (see Figure 5). An undriven TDI pin will produce the
same result as a logic 1 input level.
TDO — TEST DATA OUT (OUTPUT)
Output that is active depending on the state of the TAP
state machine (see Figure 5). Output changes in response to
the falling edge of TCK. This is the output side of the serial
registers placed between TDI and TDO.
TRST — TAP RESET
This device has a TRST pin. TRST is optional in IEEE
1149.1. Asserting the asynchronous TRST places the TAP
controller in test–logic reset state. Test–logic reset state can
also be entered by holding TMS high for five rising edges of
TCK. This type of reset does not affect the operation of the
system logic.
SHIFT–DR
EXIT1–IR
SELECT IR–SCAN
PAUSE–IR
TEST–LOGIC
RESET
EXIT1–DR
UPDATE–IR
CAPTURE–IR
SHIFT–IR
EXIT2–IR
0
RUN–TEST/
IDLE
1
PAUSE 2–DR
EXIT2–DR
PAUSE 1–DR
CAPTURE–DR
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
SELECT DR–SCAN
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 5. TAP Controller State Diagram
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