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參數資料
| 型號： | MCM69F536CTQ9R |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 32K x 36 Bit Flow-Through BurstRAM Synchronous Fast Static RAM |
| 中文描述： | 32K X 36 CACHE SRAM, 9 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數： | 5/12頁 |
| 文件大小： | 209K |
| 代理商： | MCM69F536CTQ9R |
MCM69F536C
5
MOTOROLA FAST SRAM
TRUTH TABLE
(See Notes 1 through 4)
Next Cycle
Deselect
Deselect
Deselect
Deselect
Deselect
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
Begin Write
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
NOTES: 1. X = Don’t Care. 1 = logic high. 0 = logic low.
2. Write is defined as either 1) any SBx and SW low or 2) SGW is low.
3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times.
G must also remain negated at the completion of the write cycle to ensure proper write data hold times.
Address
Used
SE1
1
0
0
X
X
0
0
X
X
1
1
X
X
1
1
X
1
0
X
1
X
1
SE2
X
X
0
X
0
1
1
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
SE3
X
1
X
1
X
0
0
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
ADSP
X
0
0
1
1
0
1
1
1
X
X
1
1
X
X
1
X
1
1
X
1
X
ADSC
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
ADV
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
1
1
X
0
0
1
1
G 3
X
X
X
X
X
0
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
DQx
High–Z
High–Z
High–Z
High–Z
High–Z
DQ
DQ
High–Z
DQ
High–Z
DQ
High–Z
DQ
High–Z
DQ
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
High–Z
Write 2, 4
X
X
X
X
X
READ
READ
READ
READ
READ
READ
READ
READ
READ
READ
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
None
None
None
None
None
External
External
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
External
Next
Next
Current
Current
LINEAR BURST ADDRESS TABLE
(LBO = VSS)
1st Address (External)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
2nd Address (Internal)
X . . . X01
X . . . X10
X . . . X11
X . . . X00
3rd Address (Internal)
X . . . X10
X . . . X11
X . . . X00
X . . . X01
4th Address (Internal)
X . . . X11
X . . . X00
X . . . X01
X . . . X10
INTERLEAVED BURST ADDRESS TABLE
(LBO = VDD)
1st Address (External)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
2nd Address (Internal)
X . . . X01
X . . . X00
X . . . X11
X . . . X10
3rd Address (Internal)
X . . . X10
X . . . X11
X . . . X00
X . . . X01
4th Address (Internal)
X . . . X11
X . . . X10
X . . . X01
X . . . X00
WRITE TRUTH TABLE
Cycle Type
SGW
SW
SBa
SBb
SBc
SBd
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write Byte a
H
L
L
H
H
H
Write Byte b
H
L
H
L
H
H
Write Byte c
H
L
H
H
L
H
Write Byte d
H
L
H
H
H
L
Write All Bytes
H
L
L
L
L
L
Write All Bytes
L
X
X
X
X
X
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