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參數資料
| 型號： | MF4 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | MF4 4th Order Switched Capacitor Butterworth Lowpass Filter |
| 中文描述： | MF4四階巴特沃斯低通開關電容濾波器 |
| 文件頁數： | 2/14頁 |
| 文件大?。?/td> | 481K |
| 代理商： | MF4 |
Block Diagram
(Continued)
Pin Descriptions
Pin
#
1
Pin
Name
CLK IN
Function
A CMOS Schmitt-trigger input to be
used with an external CMOS logic level
clock. Also used for self clocking
Schmitt-trigger oscillator (see section
1.1).
A TTL logic level clock input when in
split supply operation (
±
2.5V to
±
7V)
with L. Sh tied to system ground. This
pin becomes a low impedance output
when L. Sh is tied to V
. Also used in
conjunction with the CLK IN pin for a
self clocking Schmitt-trigger oscillator
(see section 1.1). The TTL input signal
must not exceed the supply voltages
by more than 0.2V.
Level shift pin; selects the logic
threshold levels for the clock. When
tied to V
it enables an internal tri-state
buffer stage between the Schmitt
trigger and the internal clock level shift
stage thus enabling the CLK IN
Schmitt-trigger input and making the
CLK R pin a low impedance output.
When the voltage level at this input
exceeds 25% (V
+
V
) + V
the
internal tri-state buffer is disabled
allowing the CLK R pin to become the
clock input for the internal clock
level-shift stage. The CLK R threshold
level is now 2V above the voltage on
the L. Sh pin. The CLK R pin will be
compatible with TTL logic levels when
the MF4 is operated on split supplies
with the L. Sh pin connected to system
ground.
The output of the low-pass filter. It will
typically sink 0.9 mA and source 3 mA
and swing to within 1V of each supply
rail.
The analog ground pin. This pin sets
the DC bias level for the filter section
and must be tied to the system ground
for split supply operation or to
mid-supply for single supply operation
(see section 1.2). When tied to
mid-supply this pin should be well
bypassed.
The positive and negative supply pins.
The total power supply range is 5V to
14V. Decoupling these pins with 0.1 μF
capacitors is highly recommended.
2
CLK R
3
L. Sh
5
FILTER
OUT
6
AGND
7,
4
V
+
, V
Pin
#
8
Pin
Name
FILTER
IN
Function
The input to the low-pass filter. To
minimize gain errors the source
impedance that drives this input should
be less than 2K (see section 1.3 of the
Application Hints). For single supply
operation the input signal must be
biased to mid-supply or AC coupled
through a capacitor.
www.national.com
2
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相關代理商/技術參數 |
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|---|---|
| MF-40 | 制造商:COOPER INDUSTRIES 功能描述:UNV WRNCH STANDARD 3/8 FMALE S |
| MF4001 | 制造商:CYSTEKEC 制造商全稱:Cystech Electonics Corp. 功能描述:SURFACE MOUNT DIODES |
| MF4002 | 制造商:CYSTEKEC 制造商全稱:Cystech Electonics Corp. 功能描述:SURFACE MOUNT DIODES |
| MF4003 | 制造商:CYSTEKEC 制造商全稱:Cystech Electonics Corp. 功能描述:SURFACE MOUNT DIODES |
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