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參數資料
| 型號： | MF4 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | MF4 4th Order Switched Capacitor Butterworth Lowpass Filter |
| 中文描述： | MF4四階巴特沃斯低通開關電容濾波器 |
| 文件頁數： | 5/14頁 |
| 文件大小： | 481K |
| 代理商： | MF4 |
Logic Input-Output Characteristics
(Continued)
The following specifications apply for V
= 0V (Note 7) unless otherwise specified.
Boldface limits apply for T
MIN
to T
MAX
;
all
other limits T
A
= T
J
= 25C.
Typical
(Note 10)
Tested
Limit
(Note 11)
Design
Limit
(Note 12)
Parameter
Conditions
Unit
TTL CLOCK INPUT, CLK R PIN
(Note 9)
Maximum V
IL
, Logical “0” Input Voltage
Minimum V
IH
, Logical “1” Input Voltage
Maximum Leakage Current at CLK R Pin
0.8
2.0
2.0
V
V
μA
L. Sh Pin at Mid-Supply
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. AC and DC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2:
All voltages are with respect to GND.
Note 3:
The cutoff frequency of the filter is defined as the frequency where the magnitude response is 3.01 dB less than the DC gain of the filter.
Note 4:
For
±
5V supplies the dynamic range is referenced to 2.82 Vrms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 280 μVrms for
the MF4-50. For
±
2.5V supplies the dynamic range is referenced to 1.06 Vrms (1.5V peak) where the wideband noise over a 20 kHz bandwidth is typically 130 μVrms.
Note 5:
The specifications for the MF4 have been given for a clock frequency (f
) of 250 kHz or less. Above the clock frequency the cutoff frequency begins to
deviate from the specified error band of
±
0.6% but the filter still maintains its magnitude characteristics. See Application Hints.
Note 6:
Besides checking the cutoff frequency (f
) and the stopband attenuation at 2 f
c
, two additional frequencies are used to check the magnitude response of the
filter. The magnitudes are referenced to a DC gain of 0.0 dB.
Note 7:
For simplicity all the logic levels have been referenced to V
= 0V (except for the TTL input logic levels). The logic levels will scale accordingly for
±
5V and
±
2.5V supplies.
Note 8:
The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output
to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage and then shorting that
output to the positive supply. These are worst case conditions.
Note 9:
The MF4 is operating with symmetrical split supplies and L. Sh is tied to ground.
Note 10:
Typicals are at 25C and represent most likely parametric norm.
Note 11:
Guaranteed to National’s Average Outgoing Quality Level (AOQL).
Note 12:
Guaranteed, but not 100% production tested. These limits are not used to determine outgoing quality levels.
Note 13:
Human body model; 100 pF discharged through a 1.5 k
resistor.
Note 14:
When the input voltage (V
) at any pin exceeds the power supply rails (V
<
V
or V
>
V
+
) the absolute value of current at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to four.
Note 15:
Thermal Resistance
θ
JA
(Junction to Ambient) N Package:
105C/W.
www.national.com
5
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| MF4003 | 制造商:CYSTEKEC 制造商全稱:Cystech Electonics Corp. 功能描述:SURFACE MOUNT DIODES |
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