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參數資料
| 型號： | MM74HCT193 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | CLAMP |
| 中文描述： | 同步二進制加/減計數器 |
| 文件頁數： | 3/9頁 |
| 文件大小： | 146K |
| 代理商： | MM74HCT193 |
AC Electrical Characteristics
(Note 6) V
CC
e
5V, T
A
e
25
§
C, C
L
e
15 pF, t
r
e
t
f
e
6 ns (unless otherwise specified)
Symbol
Parameter
From
(Input)
To
Conditions
Typ
Guaranteed
Limit
Units
(Output)
f
MAX
Maximum Clock
Frequency
35
MHz
t
PLH, PHL
Maximum Propagation
Delay Time
Load
QA, QB,
QC, QD
26
ns
t
PLH, PHL
Maximum Propagation
Delay Time
Data A,
B, C, D,
QA, QB,
QC, QD
25
ns
t
PLH, PHL
Maximum Propagation
Delay Time
Count-Up
or -Down
QA, QB,
QC, QD
26
ns
t
PLH, PHL
Maximum Propagation
Delay Time
Count-Up
Carry
22
ns
t
PLH, PHL
Maximum Propagation
Delay Time
Count-Dn
Borrow
22
ns
t
PLH, PHL
Maximum Propagation
Delay Time
Clear
QA, QB,
QC, QD
25
ns
AC Electrical Characteristics
(Note 6)
V
CC
e
5V,
g
10%, C
L
e
50 pF (unless otherwise specified)
From
(Input)
To
T
e
25
§
C
T
e
25
§
C
74HC
54HC
Symbol
Parameter
(Output)
T
eb
40
§
to 85
§
C
Guaranteed Limits
T
eb
55
§
to 125
§
C
Units
Typ
f
MAX
t
PLH, PHL
Maximum Clock Frequency
32
20
16
13
MHz
Maximum Propagation
Delay Time
Load
QA, QB,
QC, QD
29
44
55
66
ns
t
PLH, PHL
Maximum Propagation
Delay Time
Data A
QA, QB,
QC, QD
28
40
50
60
ns
t
PLH, PHL
Maximum Propagation
Delay Time
Count-Up
or -Down
QA, QB
QC, QD
30
43
54
65
ns
t
PLH, PHL
Maximum Propagation
Delay Time
Count-Up
Carry
25
30
38
45
ns
t
PLH, PHL
Maximum Propagation
Delay Time
Count-
Down
Borrow
25
30
38
45
ns
t
PLH, PHL
Maximum Propagation
Delay Time
Clear
QA, QB
QC, QD
28
35
44
53
ns
t
W
Minimum Clock
Pulse Width
16
25
31
38
ns
t
S
Minimum Setup Time Data
before Load-LH
20
25
30
ns
t
H
Minimum Hold Time Data
after Load-LH
b
3
5
6
8
ns
t
REM
Minimum Removal Time
Load to Count
b
2
5
6
8
ns
t
REM
Minimum Removal Time
Clear to Count
2
5
6
8
ns
t
W
Minimum Load
Pulse Width
18
20
25
30
ns
t
W
Minimum Clear
Pulse Width
8
20
25
30
ns
t
TLH, THL
C
PD
Output Rise or Fall Time
10
15
19
22
ns
Power Dissipation
Capacitance
40
pF
C
IN
Maximum Input Capacitance
5
10
10
10
pF
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
e
C
PD
V
CC2
f
a
I
CC
V
CC
, and the no load dynamic current consumption, I
s
e
C
PD
V
CC
f
a
I
CC
.
Note 6:
Refer to Section 1 for Typical MM54/74HCT AC Switchforms and Test Circuits.
3
相關PDF資料 |
PDF描述 |
|---|---|
| MM74HCT193J | CLAMP |
| MM74HCT193N | CLAMP |
| MM54HCT573 | TRI-STATE? Octal D-Type Latch / TRI-STATE Octal D-Type Flip-Flop |
| MM54HCT573N | TRI-STATE? Octal D-Type Latch / TRI-STATE Octal D-Type Flip-Flop |
| MM54HCT573WM | TRI-STATE? Octal D-Type Latch / TRI-STATE Octal D-Type Flip-Flop |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MM74HCT193J | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Synchronous Binary Up/Down Counters |
| MM74HCT193N | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Synchronous Binary Up/Down Counters |
| MM74HCT193WM | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| MM74HCT240 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer |
| MM74HCT240_05 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer |
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