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參數(shù)資料
| 型號： | MN6153UC |
| 廠商： | PANASONIC CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLL LSI with Built-In Prescaler |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 60 MHz, PDSO16 |
| 封裝： | 0.225 INCH, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大小： | 52K |
| 代理商： | MN6153UC |
For Communications Equipment
MN6153UC
Pin Descriptions
Pin No.
1
Symbol
X
IN
Function Description
Crystal oscillator connection pins:
X
IN
=Oscillator circuit input pin;
X
OUT
=Oscillator circuit output pin.
Frequency divider output signal in comparator stage.
Phase comparator input monitor.
Power supply
Low-pass filter connection pin. Use a passive filter.
Ground
Power supply pin for built-in charge pump
Frequency divider input pin in comparator stage.
Shift register clock input pin.
The chip latches data at the rising edge of the CLK signal.
Shift register data input pin.
The final two bits in the data select the write latch:
"11" for R-latch; "01" for N-latch.
Load enable signal input pin.
This is the latch-write-enable signal. It is at "H" level for write.
Power save control signal input pin.
"H" level input starts the frequency divider and places the chip in operational mode.
"L" level input places the chip in standby mode, which saves power.
The chip switches the internal charge pump output to the H-z state and the loop
is opened.
Reference frequency divider output signal.
Phase comparator input monitor.
Charge pump control signal output pin.
When frequency divider operation is stopped, this pin is at "L" level,
the internal charge pump output is in the high-impedance state, and the loop is
opened.
Phase comparator output pin for external charge pump.
(OR provides N-channel open drain output.)
2
X
OUT
3
FV
4
5
6
7
8
9
V
DD
D
OP
V
SS
V
CP
F
IN
CLK
10
DATA
11
LE
12
PS
13
FR
14
LC
15
16
OV
OR
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