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參數資料
| 型號： | MN6153UC |
| 廠商： | PANASONIC CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLL LSI with Built-In Prescaler |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 60 MHz, PDSO16 |
| 封裝： | 0.225 INCH, PLASTIC, SSOP-16 |
| 文件頁數： | 4/9頁 |
| 文件大小： | 52K |
| 代理商： | MN6153UC |
MN6153UC
For Communications Equipment
The following formula shows frequency divider operation.
F
IN
={ (16
×
N) + A}
×
(X
IN
÷ R)
where
F
IN
: VCO output frequency
N
: Setting for 14-bit programmable counter on comparator side
A
: Setting for 4-bit swallow counter on comparator side
X
IN
: Reference oscillator frequency
R
: Setting for 17-bit programmable counter on reference side
Note that N should be greater than A.
N-Side Latch Data
MSB 3 bits
14 bits
4 bits
LSB
Test data
Programmable counter
setting (N)
Swallow counter
setting (A)
MN6153 Frequency Dividing Data Settings
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