
MOSA ELECTRONICS
MS8870
DTMF Receiver
-
2
-
Pin Description
Pin #
1
2
3
Name
IN +
IN -
GS
Description
Non-inverting op-amp input.
Inverting op-amp input.
Gain select. Gives access to output of front end differential amplifier for connection
of feedback resistor.
Reference voltage output, nominally V
DD
/2 is used to bias inputs at mid-rail (see Fig.
2).
Internal connection. Must be tied to Vss.
Internal connection. Must be tied to Vss.
Clock input.
Clock output. A 3.5795 MHz crystal connected between OSC1 and OSC2 completes
the internal oscillator circuit.
Negative power supply input.
3-state output enable (input). Logic high enables the outputs Q1-Q4 Internal pull up.
3-state data output. When enable by TOE, provide the code corresponding to the last
valid tone-pair received (see Fig. 5).
Delayed steering output. Presents a logic high when a received tone-pair has been
registered and the output latch updated; return to logic low when the voltage on St/GT
falls below V
TS
t.
Early steering output. Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause
ESt to return to a logic low.
Steering input/guard time output (bi-directional). A voltage greater than V
TS
t detected
at St causes the device to register the detected tone pair and update the output latch. A
Voltage less than V
TS
t frees the device to accept a new tone pair. The GT output acts
to reset the external steering time-constant; its state is a function of ESt and the
voltage on St.
Positive power supply input.
4
V
REF
5
6
7
8
IC
IC
OSC1
OSC2
9
10
Vss
TOE
Q1-Q4
11-14
15
StD
16
ESt
17
St/GT
18
V
DD
Absolute Maximum Ratings
Parameter
Min
Max
Units
1
2
3
4
5
6
Power supply voltage V
DD
-Vss
Voltage on any pin
Current at any pin
Operating temperature
Storage temperature
Package power dissipation
6
V
V
mA
℃
℃
mW
Vss - 0.3
-40
-65
V
DD
+ 0.3
10
+85
+150
1000