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參數(shù)資料
| 型號(hào)： | MT54W4MH9BF-7.5 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 36Mb QDR⑩II SRAM 2-WORD BURST |
| 中文描述： | ⑩分配36MB四年防務(wù)審查II SRAM的2字爆 |
| 文件頁數(shù)： | 1/27頁 |
| 文件大小： | 302K |
| 代理商： | MT54W4MH9BF-7.5 |
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PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
36Mb: 1.8V V
DD
, HSTL, QDRIIb2 SRAM
MT54W2MH18B_A.fm - Rev. 9/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
2002, Micron Technology Inc.
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
1.8V V
DD
, HSTL, QDRIIb2 SRAM
ADVANCE
36Mb QDR
II SRAM
2-WORD BURST
MT54W4MH8B
MT54W4MH9B
MT54W2MH18B
MT54W1MH36B
FEATURES
DLL circuitry for accurate output data placement
Separate independent read and write data ports
with concurrent transactions
100 percent bus utilization DDR READ and WRITE
operation
Fast clock to valid data times
Full data coherency, providing most current data
Two-tick burst counter for low DDR transaction size
Double data rate operation on read and write ports
Two input clocks (K and K#) for precise DDR timing
at clock rising edges only
Two output clocks (C and C#) for precise flight time
and clock skew matching—clock and data delivered
together to receiving device
Single address bus
Simple control logic for easy depth expansion
Internally self-timed, registered writes
+1.8V core and HSTL I/O
Clock-stop capability
15mm x 17mm, 1mm pitch, 11 x 15 grid FBGA
package
User-programmable impedance output
JTAG boundary scan
GENERAL DESCRIPTION
The Micron
QDRII (Quad Data Rate) synchro-
nous, pipelined burst SRAM employs high-speed, low-
power CMOS designs using an advanced 6T CMOS
process.
The QDR architecture consists of two separate DDR
(double data rate) ports to access the memory array.
The read port has dedicated data outputs to support
READ operations. The write port has dedicated data
inputs to support WRITE operations. This architecture
eliminates the need for high-speed bus turnaround.
Access to each port is accomplished using a common
address bus. Addresses for reads and writes are latched
on rising edges of the K and K# input clocks, respec-
tively. Each address location is associated with two
words that burst sequentially into or out of the device.
OPTIONS
Clock Cycle Timing
4ns (250 MHz)
5ns (200 MHz)
6ns (167 MHz)
7.5ns (133 MHz)
Configurations
4 Meg x 8
4 Meg x 9
2 Meg x 18
1 Meg x 36
Package
165-ball, 15mm x 17mm FBGA
MARKING
1
NOTE:
1. A Part Marking Guide for the FBGA devices can be found
on Micron’s Web site—
http://www.micron.com/number-
guide
.
-4
-5
-6
-7.5
MT54W4MH8B
MT54W4MH9B
MT54W2MH18B
MT54W1MH36B
F
VALID PART NUMBERS
PART NUMBER
MT54W4MH8BF-xx
MT54W4MH9BF-xx
MT54W2MH18BF-xx
MT54W1MH36BF-xx
DESCRIPTION
4 Meg x 8, QDRIIb2 FBGA
4 Meg x 9, QDRIIb2 FBGA
2 Meg x 18, QDRIIb2 FBGA
1 Meg x 36, QDRIIb2 FBGA
Figure 1
165-Ball FBGA
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