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參數資料
| 型號： | MT90502 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Multi-Channel AAL2 SAR(多通道 ATM AAL2分段及重組設備（基于通訊總線的系統與ATM網絡的接口）) |
| 中文描述： | 多通道AAL2的特區（多通道自動柜員機AAL2的分段及重組設備（基于通訊總線的系統與空中交通管理網絡的接口）） |
| 文件頁數： | 1/11頁 |
| 文件大小： | 70K |
| 代理商： | MT90502 |
1
Features
AAL2 Segmentation Reassembly device
capable of simultaneously processing up to
1023 active CIDs (AAL2 Channel Identifier) and
1023 active VCC (Virtual Channel
Connections).
ATM VCCs can support up to 255 CIDs.
Implements AAL2 Common Part Sub-layer
(CPS) functions specified in ITU I.363.2.
CPS packet payload can support up to 64
bytes.
Can support over-subscription of 10:1.
TDM Bus supports Multiple Data Transfer
formats such as ITU G.711, G.726, G.723,
G.728 and G.729.
Support for a DSP array to perform a variety of
operations such as compression of voice.
Interface to DSP is by means of bit and byte
aligned HDLC encoding on the TDM interface.
Two UTOPIA ports: Ports A & B are
configurable as a single 8-bit UTOPIA Level 2
PHY Port with 5 ADDR lines or dual 8-bit
UTOPIA Level 1 configurable as PHY or ATM.
Third UTOPIA port for connection to an external
AAL5 SAR processor, or for chaining multiple
MT90502 devices.
TDM bus provides 32 bidirectional serial TDM
streams operating at 2.40, 4.096, and 8.192
Mbits/s.
Support clock recovery and generation.
Performs silence suppression for PCM and
ADPCM.
Capability to inject and recover CPS packets
through the CPU host processor bus.
8-bit or 16-bit microprocessor port, configurable
to Motorola or Intel timing.
IEEE 1149 (JTAG) interface.
DS5420
ISSUE 1
November 2000
Ordering Information
MT90502AG
456 Pin Plastic BGA
0 to +70
°
C
MT90502
Multi-Channel AAL2 SAR
Preliminary Information
Figure 1 - MT90502 Functional Block
SSRAM
SDRAM
Memory Bank A
SSRAM
SDRAM
Memory Bank B (Optional)
Dual Memory Controller
UTOPIA
Module
Port
A
Port
B
Port
C
RxA Port
TxA Port
RxB Port
TxB Port
RxC Port
TxC Port
TDM
Module
CPS Packet
Transmitter
CPS Packet
Receiver
AAL2 SAR
Receiver
AAL2 SAR
Transmitter
Clock
Recovery
and
Generation
CPU Interface
JTAG Interface
Clock and
Frame
Pulse
TDM Bus
4096 x64 Kbps
MT90502
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MT90502_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Multi-Channel AAL2 SAR |
| MT90502AG | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: |
| MT90503 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:2048VC AAL1 SAR |
| MT90503AG | 制造商:Microsemi Corporation 功能描述: |
| MT90520 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8-Port Primary Rate Circuit Emulation AAL1 SAR |
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