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參數資料
| 型號： | MTD15N06VL |
| 廠商： | MOTOROLA INC |
| 元件分類： | JFETs |
| 英文描述： | TMOS POWER FET 15 AMPERES 60 VOLTS RDS(on) = 0.085 OHM |
| 中文描述： | 15 A, 60 V, 0.085 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 文件頁數： | 1/10頁 |
| 文件大小： | 218K |
| 代理商： | MTD15N06VL |
1
Motorola, Inc. 1996
!
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resis-
tance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETS
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS E–FET
Surface Mount Package Available in 16 mm 13–inch/2500 Unit Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS
(TC = 25
°
C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
60
Vdc
Drain–Gate Voltage (RGS = 1.0 M
)
Gate–Source Voltage — Continuous
Gate–Source Voltage
— Single Pulse (tp
≤
50 ms)
Drain Current — Continuous @ 25
°
C
Drain Current
— Continuous @ 100
°
C
Drain Current
— Single Pulse (tp
≤
10
μ
s)
Total Power Dissipation @ 25
°
C
Derate above 25
°
C
Total Power Dissipation @ TA = 25
°
C, when mounted to minimum recommended pad size
Operating and Storage Temperature Range
60
Vdc
±
20
±
25
Vdc
Vpk
15
8.7
45
Adc
Apk
55
0.36
2.1
Watts
W/
°
C
Watts
TJ, Tstg
EAS
–55 to 175
°
C
mJ
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25
°
C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25
)
Thermal Resistance — Junction to Case
Thermal Resistance
— Junction to Ambient
Thermal Resistance
— Junction to Ambient, when mounted to minimum recommended pad size
113
R
θ
JC
R
θ
JA
R
θ
JA
TL
2.73
100
71.4
°
C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
″
from case for 10 seconds
260
°
C
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 2
Order this document
by MTD15N06V/D
SEMICONDUCTOR TECHNICAL DATA
TM
D
S
G
CASE 369A–13, Style 2
DPAK Surface Mount
TMOS POWER FET
15 AMPERES
60 VOLTS
RDS(on) = 0.12 OHM
Motorola Preferred Device
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|---|---|
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| MTD1N60E | TMOS POWER FET 1.0 AMPERE 600 VOLTS RDS(on) = 8.0 OHM |
| MTD1N80E | TMOS POWER FET 1.0 AMPERES 800 VOLTS RDS(on) = 12 OHM |
| MTD20N06HD | TMOS POWER FET 20 AMPERES 60 VOLTS RDS(on) = 0.045 OHM |
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