- 您現在的位置：買賣IC網 > PDF目錄382355 > MX812DW (Electronic Theatre Controls, Inc.) VSR CODEC WITH DRAM CONTROL PDF資料下載
參數資料
| 型號： | MX812DW |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | Codec |
| 英文描述： | VSR CODEC WITH DRAM CONTROL |
| 中文描述： | 振動時效編解碼器DRAM的控制 |
| 文件頁數： | 9/13頁 |
| 文件大小： | 115K |
| 代理商： | MX812DW |
VSR CODEC with DRAM CONTROL
9
MX812 PRELIMINARY INFORMATION
1997 MX
COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054
Doc. # 20480076.003
All trademarks and service marks are held by their respective companies.
Control Timing Information ......
Timing Specification –
Figures 6 and 7
Characteristics
See Note
Min.
Typ.
Max.
Unit
t
CSE
t
CSH
t
HIZ
t
CSOFF
t
CK
t
NXT
t
CH
t
CL
t
CDS
t
CDH
t
RDS
t
RDH
“CS-Enable to Clock-High”
2.0
–
–
μs
Last “Clock-High to CS-High”
“CS-High to Reply Output Tri-state”
“CS-High” Time between transactions
“Clock-Cycle” Time
“Inter-Byte” Time
“Serial Clock-High” Period
“Serial Clock-Low” Period
“Command Data Set-Up” Time
“Command Data Hold” Time
“Reply Data Set-Up” Time
“Repy Data Hold” Time
4.0
–
2.0
2.0
4.0
500
500
250
0
250
50.0
–
–
–
–
–
–
–
–
–
–
–
–
μs
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
2.0
–
–
–
–
–
–
–
–
–
Address Line Decoding
MA0 to MA21 are the outputs of the internal 22-bit DRAM address counter, which are time multiplexed as ‘Row’
and ‘Column’ addresses onto the DRAM address lines A0 to A10 etc., as shown below.
Memory Size (MS) Bit = “1” – 4Mbit DRAM
Pin
Row Address
Column Address
A0
MA0
MA1
A1
MA2
MA3
A2
MA4
MA5
A3
MA6
MA7
A4
MA8
MA9
A5
A6
A7
A8
A9
A10/R2
MA20
MA21
MA10
MA11
MA12
MA13
MA14 MA16
MA15 MA17
MA18
MA19
Memory Size (MS) Bit = “0” – 1Mbit DRAM(s)
Pin
Row Address
Column Address
A0
MA0
MA1
A1
MA2
MA3
A2
MA4
MA5
A3
MA6
MA7
A4
MA8
MA9
A5
A6
A7
A8
A9
MA10
MA11
MA12
MA13
MA14 MA16
MA15 MA17
MA18
MA19
MA20
0
1
MA21
x
x
RAS1
active
A10/R2
DRAM Selected
“first”
“second”
active
x = don't care
Table 4 Address Line Decoding
Sample Rate (SR) Bit
Division
Ratio
Xtal/clock Frequency (MHz)
4.032
4.0
4.096
SR =
SR =
“1”
“0”
64 kbps
128 kbps
62.5 kbps
31.25 kbps
63 kbps
31.5 kbps
64 kbps
32 kbps
Internal Clock Rate
126 kHz
Local Decoder Clock
125 kHz
128 kHz
Table 5 Sampling Clock Rates Available
相關PDF資料 |
PDF描述 |
|---|---|
| MX812J | VSR CODEC WITH DRAM CONTROL |
| MX841 | White LED Step-Up Converter |
| MX88L284AEC | Highly integration chip for Flat Panel Display application |
| MXA2500U | Ultra Low Noise, 1g Dual Axis Accelerometer with Analog Outputs |
| MXA28A | MOLDED TSSOP JEDEC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MX812J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:VSR CODEC WITH DRAM CONTROL |
| MX-818 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HIGH SPEED CMOS PROGRAMMABLE ANALOG MULTIPLEXERS |
| MX-818C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HIGH SPEED CMOS PROGRAMMABLE ANALOG MULTIPLEXERS |
| MX821 | 制造商:Applied Research Technology 功能描述:Rack Mount Eight Channel Mixer with Equalizer 制造商:APPLIED RESEARCH TECHNOLOGY 功能描述:MIXER EIGHT CHANNEL WITH EQ AND DIRECT OUTS |
| MX8217PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
發布緊急采購，3分鐘左右您將得到回復。