- 您現在的位置：買賣IC網 > PDF目錄382356 > N643GT7GI (Advanced Micro Devices, Inc.) 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory PDF資料下載
參數資料
| 型號： | N643GT7GI |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 64兆位（4個M x 16位）的CMOS 1.8伏，只有同時讀/寫，突發模式閃存 |
| 文件頁數： | 22/49頁 |
| 文件大小： | 382K |
| 代理商： | N643GT7GI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁
20
Am29BDS643G
25692A2 May 8, 2006
D A T A S H E E T
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 10 defines the valid register
command sequences. Writing
incorrect
address and
data values
or writing them in the
improper sequence
resets the device to reading array data.
All addresses are latched on the rising edge of AVD#.
All data is latched on the rising edge of WE#. Refer to
the AC Characteristics section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data in asynchronous mode. Each bank is
ready to read array data after completing an Embedded
Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-sus-
pend-read mode, after which the system can read data
from any non-erase-suspended sector. After com-
pleting a programming operation in the Erase Suspend
mode, the system may once again read array data with
the same exception. See the Erase Suspend/Erase
Resume Commands section for more information.
The system
must
issue the reset command to return a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase operation,
or if the bank is in the autoselect mode. See the next
section, Reset Command, for more information.
See also Requirements for Asynchronous
Read Operation (Non-Burst) and Requirements for
Synchronous (Burst) Read Operation in the Device
Bus Operations section for more information. The
Asynchronous Read and Synchronous/Burst Read
tables provide the read parameters, and Figures 9 and
11 show the timings.
Set Configuration Register Command Se-
quence
The configuration register command sequence
instructs the device to set a particular number of clock
cycles for the initial access in burst mode. The number
of wait states that should be programmed into the
device is directly related to the clock frequency. The
first two cycles of the command sequence are for
unlock purposes. On the third cycle, the system should
write C0h to the address associated with the intended
wait state setting (see Table 8). Address bits A16–A12
determine the setting. Note that addresses A19–A17
are shown as “0” but are actually don’t care.
Table 8.
Burst Modes
Note:
The burst mode is set in the third cycle of the Set Wait State command sequence.
Upon power up, the device defaults to the maximum
seven cycle wait state setting. It is recommended that
the wait state command sequence be written, even if
the default wait state value is desired, to ensure the
device is set as expected. A hardware reset will set the
wait state to the default setting.
Handshaking Feature
The host system should set address bits A16–A12 to
“00010” for a clock frequency of 40 MHz or to “00011”
for a clock frequency of 54 or 66 MHz, assuming con-
tinuous burst is desired in both cases.
Table 9 describes the typical number of clock cycles
(wait states) for various conditions.
Burst
Mode
Third Cycle Addresses for Wait States
Wait States
0
1
2
3
4
5
Clock Cycles
2
3
4
5
6
7
Continuous
00555h
01555h
02555h
03555h
04555h
05555h
8-word Linear
08555h
09555h
0A555h
0B555h
0C555h
0D555h
16-word Linear
10555h
11555h
12555h
13555h
14555h
15555h
32-word Linear
18555h
19555h
1A555h
1B555h
1C555h
1D555h
相關PDF資料 |
PDF描述 |
|---|---|
| N643GT7MI | 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| N80186 | High Integration 16-Bit Microprocessor iAPX86 Family |
| N80186-10 | High Integration 16-Bit Microprocessor iAPX86 Family |
| N80186-10B | High Integration 16-Bit Microprocessor iAPX86 Family |
| N80186B | High Integration 16-Bit Microprocessor iAPX86 Family |
相關代理商/技術參數 |
參數描述 |
|---|---|
| N643GT7MI | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| N6455A | 制造商:Agilent Technologies 功能描述:HARD COPY MANUAL, 4000X-SERIES OSCILLOSCOPE; Plug Type:-; Accessory Type:Hard Copy Manual; For Use With:InfiniiVision 4000 X-Series Oscilloscopes ;RoHS Compliant: NA |
| N6456A | 制造商:AGILENT TECHNOLOGIES, INC. 功能描述:Rackmount Kit for 2000 and 3000X Series Oscilloscopes 制造商:Agilent Technologies 功能描述:Bulk 制造商:Agilent Technologies 功能描述:OPTION RACK MOUNT KIT FOR X-SERIES 制造商:Agilent Technologies 功能描述:RACK MOUNT KIT; Accessory Type:Rackmount Kit; For Use With:Agilent InfiniiVision 2000X / 3000X Series Oscilloscopes ;RoHS Compliant: NA 制造商:Agilent Technologies 功能描述:Rack mount kit |
| N6457A | 制造商:AGILENT TECHNOLOGIES, INC. 功能描述:Soft Carrying Case and Front Panel Cover for 2000 and 3000X Series Scopes 制造商:Agilent Technologies 功能描述:Bulk 制造商:Agilent Technologies 功能描述:ACCESSORY SOFT CASE AND FRONT PANEL 制造商:Agilent Technologies 功能描述:ACCESSORY, SOFT CASE AND FRONT PANEL 制造商:Agilent Technologies 功能描述:SOFT CARRYING CASE AND FRONT PANEL COVER; Accessory Type:Case and Front Panel Cover; For Use With:Agilent InfiniiVision 2000X / 3000X Series Oscilloscopes ;RoHS Compliant: NA 制造商:Agilent Technologies 功能描述:Soft Carrying Case |
| N6458A-ABA | 制造商:Agilent Technologies 功能描述:Hard Copy User's Manual 2000 X series 制造商:Agilent Technologies 功能描述:N6458A / English Users Guide |
發布緊急采購，3分鐘左右您將得到回復。