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參數資料
| 型號： | NBSG53AMNR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS |
| 中文描述： | 53 SERIES, LOW SKEW CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16 |
| 封裝： | 3 X 3 MM, QFN-16 |
| 文件頁數： | 9/18頁 |
| 文件大小： | 133K |
| 代理商： | NBSG53AMNR2 |
NBSG53A
http://onsemi.com
9
Table 10. AC CHARACTERISTICS for FCBGA16
V
CC
= 0 V; V
EE
= 3.465 V to 2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V
40
°
C
25
°
C
70
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
f
max
Maximum Frequency
(See Figures 4, 6, 8, 10, and 11)
(See Figures 5, 7, 9, 10, and 11)
(Note 26)
DFF
DIV/2
8
10
8
10
8
10
GHz
t
PLH
,
t
PHL
Propagation Delay to Output Differential
CLK
→
Q, Q
(OLS = V
CC
)
(OLS = V
CC
0.4 V)
(OLS = V
CC
0.8 V, OLS = FLOAT)
**(OLS = V
EE
)
160
150
155
155
210
200
205
205
260
250
255
255
160
155
160
160
215
205
210
210
270
255
260
260
165
160
160
160
220
210
215
215
275
260
270
270
ps
SEL
→
Q, Q
(OLS = V
CC
)
(OLS = V
CC
0.4 V)
(OLS = V
CC
0.8 V, OLS = FLOAT)
**(OLS = V
EE
)
165
160
160
160
220
210
215
210
275
260
270
260
170
160
165
160
225
210
220
215
280
260
275
270
170
160
165
165
225
210
220
220
280
260
275
275
R
→
Q, Q
(OLS = V
CC
) DIV/2
(OLS = V
CC
) DFF
(OLS = V
CC
0.4 V) DIV/2
(OLS = V
CC
0.4 V) DFF
(OLS = V
CC
0.8 V, OLS = FLOAT) DIV/2
(OLS = V
CC
0.8 V, OLS = FLOAT) DFF
**(OLS = V
EE
) DIV/2
**(OLS = V
EE
) DFF
220
200
215
195
220
200
215
195
295
270
285
260
290
265
285
260
370
340
355
325
360
330
355
325
225
205
220
200
220
200
220
200
300
275
290
265
295
270
290
265
375
345
360
330
370
340
360
330
225
205
220
200
220
200
220
200
300
275
290
265
295
270
290
265
375
345
360
330
370
340
360
330
t
SKEW
Duty Cycle Skew (Notes 27 and 29)
DFF
5
20
5
20
5
20
ps
t
JITTER
RMS Random Clock Jitter
f
in
8 GHz
(See Figures 4 and 6) (Note 26)
PeaktoPeak Data Dependent Jitter
f
in
= 8 Gb/s
0.5
1.5
0.5
TBD
1.5
0.5
1.5
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 28)
75
2600
75
2600
75
2600
mV
t
r
t
f
Output Rise/Fall Times (20% 80%)
@ 1 GHz
Q, Q
(OLS = V
CC
)
(OLS = V
CC
0.4 V)
(OLS = V
CC
0.8 V, OLS = FLOAT)
**(OLS = V
EE
)
30
20
25
25
50
40
45
45
65
60
65
65
30
20
25
25
50
40
45
45
65
60
65
65
30
20
25
25
50
40
45
45
65
60
65
65
ps
t
s
t
h
Setup Time
D
→
CLK
30
14
30
10
30
13
ps
Hold Time
D
→
CLK
25
12
25
7
25
9
ps
t
rr
Reset Recovery
DFF, DIV/2
40
9
40
12
40
10
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
26.Measured using a 500 mV source, 50% duty cycle clock source. Repetitive 1010 input data pattern. All outputs loaded with 50 to
V
CC
2.0 V. Input edge rates is 40 ps (20% 80%).
27.See Figure 14. t
SKEW
= |t
PLH
t
PHL
| for a nominal 50% differential clock input waveform.
28.V
INPP
(MAX) cannot exceed V
CC
V
EE
(Applicable only when V
CC
V
EE
< 2600 mV).
29.See Figure 10. Duty Cycle % vs. Frequency.
**When an output level of 400 mV is desired and V
CC
V
EE
> 3.0 V, a 2 k resistor should be connected from OLS to V
EE
.
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