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參數資料
型號: NCP1207DR2
廠商: ON SEMICONDUCTOR
元件分類: 穩壓器
英文描述: PWM Current-Mode Controller for Free Running Quasi-Resonant Operation
中文描述: 0.5 A SWITCHING CONTROLLER, PDSO8
封裝: SOIC-8
文件頁數: 9/18頁
文件大小: 202K
代理商: NCP1207DR2
NCP1207
http://onsemi.com
9
The DSS behavior actually depends on the internal IC
consumption and the MOSFET’s gate charge Qg. If we
select a MOSFET like the MTP2N60E, Qg equals 22 nC
(max). With a maximum switching frequency selected at
75 kHz, the average power necessary to drive the MOSFET
(excluding the driver efficiency and neglecting various
voltage drops) is:
Fsw
Qg
V
CC
with:
Fsw = maximum switching frequency
Qg = MOSFET’s gate charge
V
CC
= V
GS
level applied to the gate
To obtain the output current, simply divide this result by
V
CC
: I
driver
= F
SW
Qg = 1.6 mA. The total standby power
consumption at noload will therefore heavily rely on the
internal IC consumption plus the above driving current
(altered by the driver’s efficiency). Suppose that the IC is
supplied from a 350 VDC line. The current flowing through
pin 8 is a direct image of the NCP1207 consumption
(neglecting the switching losses of the HV current source).
If I
CC2
equals 2.3 mA @ T
J
= 60
°
C, then the power
dissipated (lost) by the IC is simply: 350 V x 2.3 mA =
805 mW. For design and reliability reasons, it would be
interested to reduce this source of wasted power that
increase the die temperature. This can be achieved by using
different methods:
1. Use a MOSFET with lower gate charge Qg.
2. Connect pin 8 through a diode (1N4007 typically) to
one of the mains input. The average value on pin 8
becomes
VmainsPEAK
example drops to: 223 V x 2.3 mA = 512 mW. If a
resistor is installed between the mains and the diode,
you further force the dissipation to migrate from the
package to the resistor. The resistor value should
account for lowline startups.
2
. Our power contribution
1
2
3
4
8
7
6
5
HV
1N4007
MAINS
6
5
1
2
Figure 17. A simple diode naturally reduces the
average voltage on pin 8
C
bulk
When using Figure 17 option, it is important to check
the absence of any negative ringing that could occur
on pin 8. The resistor in series should help to damp
any parasitic LC network that would ring when
suddenly applying the power to the IC. Also, since
the power disappears during 10 ms (halfwave
rectification), CV
CC
should be calculated to supply
the IC during these holes in the supply
3. Permanently force the V
CC
level above V
CCH
with
an auxiliary winding. It will automatically
disconnect the internal startup source and the IC will
be fully selfsupplied from this winding. Again, the
total power drawn from the mains will significantly
decrease. Make sure the auxiliary voltage never
exceeds the 16 V limit.
Skipping Cycle Mode
The NCP1207 automatically skips switching cycles when
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the socalled skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 18) and
follows the following formula:
1
2
Lp = primary inductance
Fsw = switching frequency within the burst
Ip = peak current at which skip cycle occurs
D
burst
= burst width / burst recurrence
Lp
Ip
2
Fsw
Dburst
with:
Figure 18. The skip cycle takes place at low peak
currents which guaranties noise free operation
0
300
200
100
MAX PEAK
CURRENT
WIDTH
RECURRENCE
SKIP CYCLE
CURRENT LIMIT
NORMAL CURRENT
MODE OPERATION
C
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