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參數資料
| 型號： | NCP1605DR2G |
| 廠商： | ON Semiconductor |
| 文件頁數： | 25/32頁 |
| 文件大?。?/td> | 745K |
| 描述： | IC PFC CONTROLLER CCM/DCM 16SOIC |
| 標準包裝： | 1 |
| 系列： | Soft-Skip™ |
| 模式： | 臨界傳導（CRM），間歇導電（DCM） |
| 頻率 - 開關： | 250kHz |
| 電流 - 啟動： | 12mA |
| 電源電壓： | 10 V ~ 20 V |
| 工作溫度： | 0°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 標準包裝 |
| 其它名稱： | NCP1605DR2GOSDKR |
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NCP1605, NCP1605A, NCP1605B
http://onsemi.com
25
Figure 64. Standby Management
300 mV
95.5% of the Regulation Level
Drive
V
OUT
L
SKIP
V
OUT
V
Pin1
V
CONTROL
Remark:
" Skip cycle is not allowed during the PFC startup phase
to avoid that it interferes with the softstart. That is why,
skip cycle is enabled only when pfcOK is high.
" Each working phase of the burst mode starts smoothly as
Pin 3 is grounded at the beginning of it. This softstart
capability is effective to avoid the audible noise that
could possibly result from such a burst operation.
" The circuit leaves the standby mode when the output
voltage goes below 95.5% of its regulation level and
V
Pin1
is above 330 mV (300 mV + 30 mV hysteresis).
Oscillator / Synchronization Section
The oscillator generates the clock signal to set the PWM
latch and turn the MOSFET on. The oscillator frequency is
set by the capacitor that is applied to Pin 8. Typically,
820 pF force about 60 kHz. The maximum allowable
oscillator frequency is 250 kHz. The clock frequency can
also be driven by an external synchronization signal.
This block contains two main parts (refer to Figure 66):
" The arrangement that consists of charging/discharging
current sources, a switch and a comparator. When used
in oscillator mode, a capacitor is connected between
Pin 8 and ground. A current source (100 mA) charges the
Pin 8 capacitor until its voltage exceeds VoscH. At that
moment, the comparator ( COMP_OSC ) turns high and
activates the discharge current source (200 mA). As a
consequence, Pin 8 actually sinks 100 mA that discharge
the oscillator capacitor to VoscL. At that moment, the
comparator turns low and initiates a new charge phase. If
the circuit is to be externally triggered, the
synchronization signal must cross VoscL and VoscH to
properly turn on and off the COMP_OSC comparator.
Also the synchronization signal must be low impedance
enough not to be distorted by the Pin 8 source and sink
currents.
" The storing circuitry that contains a latch and some
gates. The raising edge of the COMP_OSC output sets
the CLOCK Generation latch to turn high the CLK
signal. If the timing capacitor of Pin 7 is properly
discharged (V
Pin4
<50 mV leading to C
T
OK high), the
PWM block is ready for a new cycle and CLK can
force the signal V
SET
in high state. As a consequence,
the PWM latch sets. In addition, V
SET
resets the
CLOCK Generation latch to make it ready for the next
oscillator cycle. The two inverters of Figure 66, simply
generate some delay to ensure that V
SET
keeps high
long enough to set the PWM latch and reset the
CLOCK Generation latch (longer delay than that
produced by the two gates, may actually be necessary).
The oscillator / Synchronization block is designed to set the
switching frequency.
However, the coil current can possibly be non zero at the
end of a clock period and the circuit would enter Continuous
Conduction Mode (CCM) if the MOSFET turned on in that
moment. In order to prevent CCM, the storing circuitry of
the oscillator / synchronization block, memorizes the
COMP_OSC rising edge (thanks to the CLOCK
Generation latch) and delays the next MOSFET conduction
time until the coil current has totally vanished (that is until the
signal DT is high DT is generated by the current sense
block so that it is high during the deadtime and low
otherwise). In other words, CRM operation is obtained (refer
to Figure 65).
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