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參數資料
| 型號： | NCP1651DR2G |
| 廠商： | ON Semiconductor |
| 文件頁數： | 15/32頁 |
| 文件大小： | 779K |
| 描述： | IC PFC CONTROLLER CCM/DCM 16SOIC |
| 標準包裝： | 1 |
| 模式： | 連續導電（CCM），間歇導電（DCM） |
| 頻率 - 開關： | 25kHz ~ 250kHz |
| 電流 - 啟動： | 8.5mA |
| 電源電壓： | 10 V ~ 18 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 標準包裝 |
| 其它名稱： | NCP1651DR2GOSDKR |
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NCP1651
http://onsemi.com
15
Results
ItisclearfromtheresultofouranalysisthataflybackPFC
converter operating in CCM has half the peak current and
one tenth the fundamental (100 kHz) harmonic current
compared to a flyback PFC converter operating in DCM.
TheresultsarelowerconductionlossesintheMOSFET,and
secondaryrectifyingdiode,andasmallerinputEMIfilterif
the designer needs to meet the requirements C.I.S.P.R.
conducted emission levels. On the down side to CCM
operation, the flyback transformer will belarger becauseof
the required higher primary inductance.
The advantages to operating in DCM include lower
switchinglossesbecausethecurrentfallstozeropriortothe
next switching cycle, and smaller transformer size.
It will ultimately be up to the designer to perform a
trade- -off study to determine which topology, Boost versus
Flyback, Continuous versus Discontinuous Mode of
operation will meet all the system performance
requirements. But the recent introduction of the NCP1651
allows the system designer one additional option.
ForanaveragecurrentmodeflybacktopologybasedPFC
converter,determiningthetransformerparameters(primary
inductance and turns ratio) involves several trade- -offs.
These include peak- -to- -average current ratio (higher
inductance or turns ratio result in lower peak current),
switching losses (higher turns ratio leads to higher peak
voltage and higher switching losses), CCM vs. DCM
operation (lower values of turns ratio or higher values of
inductanceextendtheCCMrange)andrangeofdutycycles
overtheoperationallineandloadrange.ONSemiconductor
has designed an Excel- -based spreadsheet to help design
withtheNCP1651andbalancethesetrade- -offs.Thedesign
aid is downloadable free- -of- -charge from our website
(www.onsemi.com).
The ideal solution depends on the specific application
requirements and the relative priority between factors such
as THD performance, cost, size and efficiency. The design
aid allows the designer to consider different scenarios and
settleonthebestsolutionfoeagivenapplication.Following
guidelines will help in settling towards the most feasible
solution.
1. Turns Ratio Limitations: While higher turns ratio
can limit the reflected primary voltage and current,
it is constrained by the inherent limitations of the
flyback topology. A turns ratio of higher than 20:1
will result in very high leakage inductance and
lead to high leakage spikes on the primary switch.
Thus, practical application of this approach is
restricted to output voltages 12 V and above.
2. CCM Operation: The NCP1651 is designed to
operate in both CCM and DCM modes. However,
the CCM operation results in much better THD
than the DCM operation. Thus, it is recommended
that the circuit be designed to operate in CCM at
the specified test condition for harmonics
compliance (typically at 230 V, full load). Please
keep in mind that at or near zero crossing
(<10 deg angle), it is neither necessary nor feasible
to maintain CCM operation.
3. Following key governing equations have been
incorporated in the design aid:
PFC Operation
ThebasicPWMfunctionoftheNCP1651iscontrolledby
a small block of circuitry, which comprises the DC
regulation loop and the PFC circuit. These components are
shown in Figure 30.
There are three inputs to this loop. They are the fullwave
rectified sinewave, the instantaneous input current and the
error signal at the FB/SD pin.
Theinputcurrentisforcedtomaintainanearunitypower
factor due to the control of the AC error amplifier. This
amplifier uses information from the AC input voltage and
theACinputcurrenttocontrolthepowerswitchinamanner
that gives good DC regulation as well as excellent power
factor.
Thereferencemultipliersetsareferencelevelfortheinput
fullwave rectified sinewave. One of its inputs is connected
to a scaled down fullwave rectified sinewave, and the other
receives the error signal which has been converted to a
current. The error signal adjusts the level of the fullwave
rectified sinewave on the multipliers output without
distorting it. To accomplish this, it is necessary for the
bandwidth of the DC error amp to be less than twice the
lowestlinefrequency.Typicallyitissetatafactoroftenless
than the rectified frequency (e.g. for a 60 Hz input, the
bandwidth would be 12 Hz).
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