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參數資料
型號: NCP1651DR2G
廠商: ON Semiconductor
文件頁數: 31/32頁
文件大小: 779K
描述: IC PFC CONTROLLER CCM/DCM 16SOIC
標準包裝: 1
模式: 連續導電(CCM),間歇導電(DCM)
頻率 - 開關: 25kHz ~ 250kHz
電流 - 啟動: 8.5mA
電源電壓: 10 V ~ 18 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 16-SOIC
包裝: 標準包裝
其它名稱: NCP1651DR2GOSDKR
NCP1651
http://onsemi.com
31
Figure 45. Forward Gain Plot
FREQUENCY (Hz)
0.01
0.1
1
100
1000
40
30
25
20
0
- -10
- -15
10
- -5
5
10
15
35
For a crossover frequency of 10 Hz, the error amplifier
needs a gain of - -25 dB at 10 Hz, since the forward gain is
equalto25dBatthisfrequency.Thehighfrequencygainof
the error amplifier is:
A
Vhf
= R
fb
/ R
dc1
Where R
dc1
is the output voltage divider resistor that is
connectedfromtheoutputoftheconvertertotheinputofthe
erroramplifier.IftheoutputcircuitofFigure42isused,R
dc1
would be 9.31 k + 453 ? or 9.76 k? A gain of - -25 dB is
equal to a divider ratio of:
A
V
= 10
(- -25/20)
= 0.056
so, R
fb
/ R
dc1
= 0.056
or, R
fb
= 0.056 x 9.76 k?= 546 ?/DIV>
The closest standard value resistor is 560 ?
To offset the 2 Hz pole of the output filter, the error
amplifier should have a zero of 2 Hz or slightly higher. For
a 2 Hz zero, the compensation capacitor, C
fb
can be
calculated by:
C
fb
=
1
2 ?R
fb
3 Hz
= 95 mF
100 mF is the closest standard value capacitor and would
beagoodchoice.Thissolutionwillprovideaphasemargin
ofcloseto90?Inpracticethevalueofcapacitancecouldbe
cut in half or more and probably remain stable. This can be
tested in the circuit, or simulated with a model in SPICE or
a similar analysis program.
Thegainandphaseplotsofthecompletedloopareshown
in Figures 46 and 47. These include the effects of all of the
stages shown.
Figure 46. Loop Gain Plot
FREQUENCY (Hz)
0.01
0.1
1
100
1000
80
60
40
20
0
- -20
- -40
10
Figure 47. Loop Phase Plot
FREQUENCY (Hz)
0.01
0.1
1
100
1000
- -75
- -105
- -165
- -180
10
- -150
- -135
- -120
- -90
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