- 您現在的位置：買賣IC網 > PDF目錄382380 > PCD5003 (NXP Semiconductors N.V.) Advanced POCSAG Paging Decoder PDF資料下載
參數資料
| 型號： | PCD5003 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Advanced POCSAG Paging Decoder |
| 中文描述： | 高級尋呼POCSAG碼解碼器 |
| 文件頁數： | 17/44頁 |
| 文件大小： | 187K |
| 代理商： | PCD5003 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
1997 Jun 24
17
Philips Semiconductors
Product specification
Advanced POCSAG Paging Decoder
PCD5003
Table 13
Index register
Notes
1.
2.
The index register only uses the least significant nibble, the upper 4 bits are ignored.
Writing to registers 0B to 0F has no effect, reading produces meaningless data.
ADDRESS
(1)
REGISTER FUNCTION
ACCESS
00H
00H
01H
02H
03H
04H
05H
05H
06H
07H
08H
09H
0AH
status
control
R
W
real time clock: seconds
real time clock:
1
100
second
alert cadence
alert set-up
periodic interrupt modulus
periodic interrupt counter
RAM write address pointer
EEPROM address pointer
RAM read address pointer
RAM data output
EEPROM data input/output
unused
R/W
R/W
W
W
W
R
R
R/W
R/W
R
R/W
note 2
0BH to 0FH
7.24
External interrupt
The PCD5003 can signal events to an external controller
via an interrupt signal on output INT. The interrupt polarity
is programmable via SPF programming. The interrupt
source is shown in the status register.
Interrupts are generated by the following events (more
than one event possible):
Call data available for output (bit D2)
SRAM pointers becoming equal (bit D3)
Expiry of periodic time-out (bit D7)
Expiry of alert time-out (bit D4)
Change of state in out-of-range indicator (bit D5)
Change of state in battery-low indicator or in receiver
control output RXE (bit D6).
Immediate interrupts are generated by status bits D3, D4,
D6 (RXE monitoring) and D7. Bits D2, D5 and D6 (BAT
monitoring) generate interrupts as soon as the receiver is
disabled (RXE = 0).
When call data is available (D2 = 1) but the receiver
remains switched on, an interrupt is generated at the next
sync word position.
The interrupt output INT is reset after completion of a
status read operation.
7.25
Status/Control register
The status/control register consists of two independent
registers, one for reading (status) and one for writing
(control).
The status register shows the current operating condition
of the decoder and the cause(s) of an external interrupt.
The control register activates/deactivates certain
functions. Tables 14 and 15 show the bit allocations of
both registers.
All status bits will be reset after a status read operation
except for the out-of-range, battery-low and receiver
enable indicator bits (see note 1 to Table 14).
Status bit D0 is set when call reception is started by
detection of an enabled RIC (user address). This does not
generate an interrupt.
相關PDF資料 |
PDF描述 |
|---|---|
| PCD5003H | Advanced POCSAG Paging Decoder |
| PCD5008 | FLEX Pager Decoder |
| PCD5008H | FLEX Pager Decoder |
| PCD5013 | FLEX roaming decoder II |
| PCD5013H | FLEX roaming decoder II |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PCD5003A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for POCSAG |
| PCD5003AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for POCSAG |
| PCD5003H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder |
| PCD5003HB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5003U/10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder |
發布緊急采購，3分鐘左右您將得到回復。