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參數資料
| 型號： | PCD5003 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Advanced POCSAG Paging Decoder |
| 中文描述： | 高級尋呼POCSAG碼解碼器 |
| 文件頁數： | 6/44頁 |
| 文件大小： | 187K |
| 代理商： | PCD5003 |
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1997 Jun 24
6
Philips Semiconductors
Product specification
Advanced POCSAG Paging Decoder
PCD5003
7
FUNCTIONAL DESCRIPTION
7.1
Introduction
The PCD5003 is a very low power decoder and pager
controller specifically designed for use in new generation
radio pagers. The architecture of the PCD5003 allows for
flexible application in a wide variety of radio pager designs.
The PCD5003 is fully compatible with “CCIR Radio paging
Code No. 1”(also known as the POCSAG code) operating
at data rates of 512, 1200 and 2400 bits/s using a single
oscillator crystal of 76.8 kHz.
In addition to the standard POCSAG sync word the
PCD5003 is also capable of recognizing up to 4 User
Programmable Sync Words (UPSWs). This permits the
reception of both private services and POCSAG
transmissions via the same radio channel.
Used together with the Philips UAA2080 or UAA2082
paging receiver, the PCD5003 offers a highly
sophisticated, miniature solution for the radio paging
market. Control of an RF synthesizer circuit is also
provided to ease alignment and channel selection.
On-chip EEPROM provides storage for user addresses
(Receiver Identity Codes or RICs) and Special
Programmed Functions (SPFs), which eliminates the need
for external storage devices and interconnection. For other
non-volatile storage 20 bytes of general purpose
EEPROM are available. The low EEPROM programming
voltage makes the PCD5003 well- suited for ‘over-the-air’
programming/reprogramming.
On request from an external controlling device or
automatically (by SPF programming), the PCD5003 will
provide standard POCSAG alert cadences by driving a
standard acoustic ‘beeper’. Non-standard alert cadences
may be generated via a cadence register or a dedicated
control input.
The PCD5003 can also produce a HIGH level acoustic
alert as well as drive an LED indicator and a vibrator motor
via external bipolar transistors.
The PCD5003 contains a low-power, high-efficiency
voltage converter (doubler) designed to provide a higher
voltage supply to LCD drivers or microcontrollers.
In addition, an independent level shifted interface is
provided allowing communication to a microcontroller
operating at a higher voltage than the PCD5003.
Interface to such an external device is provided by an
I
2
C-bus which allows received call identity and message
data, data for the programming of the internal EEPROM,
alert control and pager status information to be transferred
between the devices. Pager status includes features
provided by the PCD5003 such as battery-low and
out-of-range indications. A dedicated interrupt line
minimizes the required microcontroller activity.
A selectable low frequency timing reference is provided for
use in real time clock functions.
Data synchronization is achieved by the Philips patented
ACCESS
algorithm ensuring that maximum advantage is
made of the POCSAG code structure particularly in fading
radio signal conditions. The algorithm allows for data
synchronization without preamble detection whilst
minimizing battery power consumption.
Random and (optional) burst error correction techniques
are applied to the received data to optimize on call success
rate without increasing falsing rate beyond specified
POCSAG levels.
7.2
The POCSAG paging code
A transmission using the “CCIR Radio paging Code No. 1”
(POCSAG code) is constructed in accordance with the
following rules (see Fig.3).
The transmission is started by sending a
preamble
,
consisting of at least 576 continuously alternating bits
(10101010...). The preamble is followed by an arbitrary
number of batch blocks. Only complete batches are
transmitted.
Each
batch
comprises 17 codewords of 32 bits each.
The first codeword is a synchronization codeword with a
fixed pattern. The
sync
word is followed by 8 frames
(0 to 7)
of 2 codewords each, containing message information.
A codeword in a frame can either be an address, message
or idle codeword.
Idle
codewords also have a fixed pattern and are used to
fill empty frames or to separate messages.
Address
codewords are identified by an MSB of logic 0
and are coded as shown in Fig.3. A user address or RIC
consists of 21 bits. Only the upper 18 bits are encoded in
the address codeword (bits 2 to 19).
The lower 3 bits designate the frame number (0 to 7) in
which the address is transmitted.
Four different
call types
(‘numeric’, ‘alphanumeric’ and
two ‘alert only’ types) can be distinguished on each user
address. The call type is determined by two function bits in
the address codeword (bits 20 and 21), as shown in
Table 1.
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| PCD5003H | Advanced POCSAG Paging Decoder |
| PCD5008 | FLEX Pager Decoder |
| PCD5008H | FLEX Pager Decoder |
| PCD5013 | FLEX roaming decoder II |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PCD5003A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for POCSAG |
| PCD5003AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for POCSAG |
| PCD5003H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder |
| PCD5003HB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5003U/10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG Paging Decoder |
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