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參數資料
| 型號： | PCM3002E |
| 元件分類： | Codec |
| 英文描述： | 16-/20-Bit Single-Ended Analog Input/Output STEREO AUDIO CODECs |
| 中文描述： | 16-/20-Bit單端模擬輸入/輸出立體聲編解碼器 |
| 文件頁數： | 15/23頁 |
| 文件大小： | 206K |
| 代理商： | PCM3002E |
15
PCM3002/3003
SYSTEM CLOCK
The system clock for PCM3002/3003 must be either 256f
S
,
384f
S
or 512f
S
, where f
S
is the audio sampling frequency. The
system clock should be provided at the SYSCLK input (pin 9).
The PCM3002/3003 also has a system clock detection circuit
which automatically senses if the system clock is operating at
256f
S
, 384f
S
, or 512f
S
. When 384f
S
or 512f
S
system clock is
used, the clock is divided into 256f
S
automatically. The 256f
S
clock is used to operate the digital filters and the delta-sigma
modulators.
Table I lists the relationship of typical sampling frequencies
and system clock frequencies, while Figure 5 illustrates the
system clock timing.
POWER-ON RESET
Both the PCM3002 and PCM3003 have internal power-on
reset circuitry. Power-on reset occurs when system clock
(SYSCLK) is active and V
DD
> 2.2V. For the PCM3003, the
SYSCLK must complete a minimum of 3 complete cycles
prior to V
DD
> 2.2V to ensure proper reset operation. The
initialization sequence requires 1024 SYSCLK cycles for
completion, as shown in Figure 6. Figure 8 shows the state
of the DAC and ADC outputs during and after the reset
sequence.
EXTERNAL RESET
The PCM3002 includes a reset input, RST (pin 7), while the
PCM3003 utilizes both PDAD (pin 7) and PDDA (pin 8) for
external reset control. As shown in Figure 7, the external
reset signal must drive RST or PDAD/PDDA low for a
minimum of 40 nanoseconds while SYSCLK is active in
order to initiate the reset sequence. Initialization starts on the
rising edge of RST or PDAD/PDDA, and requires 1024
SYSCLK cycles for completion. Figure 8 shows the state of
the DAC and ADC outputs during and after the reset se-
quence.
SAMPLING RATE FREQUENCY
(kHz)
SYSTEM CLOCK FREQUENCY
(MHz)
256f
S
384f
S
512f
S
32
44.1
48
8.1920
11.2896
12.2880
12.2880
16.9340
18.4320
16.3840
22.5792
24.5760
TABLE I. System Clock Frequencies.
System Clock Pulse Width High
t
SCKH
t
SCKL
12ns
(min)
System Clock Pulse Width Low
12ns
(min)
t
SCKH
t
SCKL
1/256f
S
,1/384f
S
,or 1/512f
S
0.7V
"H"
SYSCLK
"L"
0.3V
DD
FIGURE 5. System Clock Timing.
1024 System Clock Periods
Reset
Reset Removal
2.4V
2.2V
2.0V
V
DD
Internal Reset
SYSCLK
FIGURE 6. Internal Power-On Reset Timing.
1024 System Clock Periods
Reset
Reset Removal
SYSCLK
Internal Reset
RST
or
PDAD and PDDA
t
RST
t
RST
= 40ns minimum
FIGURE 7. External Forced Reset Timing.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PCM3002E | 制造商:Texas Instruments 功能描述:AUDIO CODEC IC 制造商:Texas Instruments 功能描述:IC, AUDIO CODEC, 20BIT, 48KHZ, SSOP-24 |
| PCM3002E/2K | 功能描述:接口—CODEC 16/20-Bit Sngl-end Anlg I/O Ster Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3002E/2KG4 | 功能描述:接口—CODEC 16/20-Bit Sngl-end Anlg I/O Ster Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3002EG | 功能描述:接口—CODEC 16/20-Bit Sngl-end Anlg I/O Ster Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3002EG/2K | 功能描述:接口—CODEC 16/20-Bit Sngl-end Anlg I/O Ster Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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