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參數資料
| 型號： | PCM3002E |
| 元件分類： | Codec |
| 英文描述： | 16-/20-Bit Single-Ended Analog Input/Output STEREO AUDIO CODECs |
| 中文描述： | 16-/20-Bit單端模擬輸入/輸出立體聲編解碼器 |
| 文件頁數： | 16/23頁 |
| 文件大小： | 206K |
| 代理商： | PCM3002E |
PCM3002/3003
16
synchronization occurs followed by t
ADCDLY2
delay time. If
LRCIN is synchronized with 5 or less bit clocks to the system
clock, operation will be normal. Figure 9 illustrates the effects
on the output when synchronization is lost. Before the outputs
are forced to bipolar zero (<1/f
S
seconds), the outputs are not
defined and some noise may occur. During the transitions
between normal data and undefined states, the output has
discontinuities, which will cause output noise.
ZERO FLAG OUTPUT: PCM3002 ONLY
Pin 16 is an open-drain output, used as the infinite zero
detection flag on the PCM3002 only. When input data is
continuously zero for 65,536 BCKIN cycles, ZFLG is LOW,
otherwise, ZFLG is in a high-impedance state.
Synchronous
Asynchronous
Synchronization
Lost
Resynchronization
within
1/f
S
Synchronous
Normal
Normal
t
ADCDLY2
(32/f
S
)
t
DACDLY2
(32/f
S
)
Undefined Data
V
(= 1/2 x V
CC
)
Undefined Data
State of
Synchronization
DAC V
OUT
Normal
Normal
(1 )
Zero
ADC DOUT
NOTES: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR
with 200ms time constant) appears initially.
Reset
Power Down
GND
V
COM
(0.5V
CC
)
Ready/Operation
Internal Reset
or Power Down
ADC DOUT
DAC V
OUT
Zero
Zero
Normal Data
(1)
t
ADCDLY1
(18436/f
S
)
t
DACDLY1
(16384/f
S
)
Reset Removal or Power Down OFF
NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR
with 200ms time constant) appears initially.
SYNCHRONIZATION WITH THE DIGITAL
AUDIO SYSTEM
The PCM3002/3003 operates with LRCIN synchronized to
the system clock. PCM3002/3003 does not require any spe-
cific phase relationship between LRCIN and the system
clock, but there must be synchronization. If the synchroniza-
tion between the system clock and LRCIN changes more than
6 bit clocks (BCKIN) during one sample (LRCIN) period
because of phase jitter on LRCIN, internal operation of the
DAC will stop within 1/f
S
, and the analog output will be
forced to bipolar zero (0.5V
CC
) until the system clock is re-
synchronized to LRCIN followed by t
DACDLY2
delay time.
Internal operation of the ADC will also stop within 1/f
S
, and
the digital output codes will be set to bipolar zero until re-
FIGURE 8. DAC Output and ADC Output for Reset and Power Down.
FIGURE 9. DAC Output and ADC Output for Loss of Synchronization.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PCM3002E | 制造商:Texas Instruments 功能描述:AUDIO CODEC IC 制造商:Texas Instruments 功能描述:IC, AUDIO CODEC, 20BIT, 48KHZ, SSOP-24 |
| PCM3002E/2K | 功能描述:接口—CODEC 16/20-Bit Sngl-end Anlg I/O Ster Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3002E/2KG4 | 功能描述:接口—CODEC 16/20-Bit Sngl-end Anlg I/O Ster Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3002EG | 功能描述:接口—CODEC 16/20-Bit Sngl-end Anlg I/O Ster Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| PCM3002EG/2K | 功能描述:接口—CODEC 16/20-Bit Sngl-end Anlg I/O Ster Codec RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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