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參數(shù)資料
| 型號： | PHU2N50E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | PowerMOS transistors Avalanche energy rated |
| 中文描述： | 2 A, 500 V, 5 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-251 |
| 封裝： | PLASTIC, IPAK-3 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大小： | 64K |
| 代理商： | PHU2N50E |
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHU2N50E
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
E
AS
Non-repetitive avalanche
energy
CONDITIONS
Unclamped inductive load, I
= 1.26 A;
t
p
= 0.2 ms; T
j
prior to avalanche = 25C;
V
≤
50 V; R
GS
= 50
; V
GS
= 10 V; refer
to fig:17
MIN.
-
MAX.
82
UNIT
mJ
E
AR
Repetitive avalanche energy
1
I
= 2 A; t
= 2.5
μ
s; T
prior to
-
3.3
mJ
avalanche = 25C; R
GS
= 50
; V
GS
= 10 V;
refer to fig:18
I
AS
, I
AR
Repetitive and non-repetitive
avalanche current
-
2
A
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-mb
Thermal resistance junction
to mounting base
R
th j-a
Thermal resistance junction
to ambient
CONDITIONS
MIN.
-
TYP. MAX. UNIT
-
2.5
K/W
In free air
-
70
-
K/W
ELECTRICAL CHARACTERISTICS
T
j
= 25 C unless otherwise specified
SYMBOL PARAMETER
V
(BR)DSS
Drain-source breakdown
voltage
V
(BR)DSS
/ Drain-source breakdown
T
j
voltage temperature
coefficient
R
DS(ON)
Drain-source on resistance
V
GS(TO)
Gate threshold voltage
g
fs
Forward transconductance
I
DSS
Drain-source leakage current V
DS
= 500 V; V
GS
= 0 V
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA
MIN.
500
TYP. MAX. UNIT
-
-
V
V
DS
= V
GS
; I
D
= 0.25 mA
-
0.1
-
%/K
V
GS
= 10 V; I
= 1 A
V
DS
= V
; I
D
= 0.25 mA
V
DS
= 30 V; I
= 1 A
-
3.1
3.0
1.3
1
77
10
20
2
12
10
20
60
20
3.5
7.5
5
V
S
μ
A
μ
A
nA
nC
nC
nC
ns
ns
ns
ns
nH
nH
2.0
0.5
-
-
-
-
-
-
-
-
-
-
-
-
4.0
-
25
250
200
25
3
15
-
-
-
-
-
-
V
DS
= 500 V; V
GS
= 0 V; T
j
= 125 C
I
GSS
Q
g(tot)
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
L
d
L
s
Gate-source leakage current V
GS
=
±
30 V; V
DS
= 0 V
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Internal drain inductance
Internal source inductance
I
D
= 2 A; V
DD
= 400 V; V
GS
= 10 V
V
DD
= 250 V; R
D
= 120
;
R
G
= 24
Measured from tab to centre of die
Measured from source lead to source
bond pad
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
C
iss
C
oss
C
rss
Input capacitance
Output capacitance
Feedback capacitance
-
-
-
236
40
22
-
-
-
pF
pF
pF
1
pulse width and repetition rate limited by T
j
max.
May 1999
2
Rev 1.000
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