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參數(shù)資料
| 型號： | PI6C2502WE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK DRIVER 8-SOIC |
| 標準包裝： | 97 |
| 類型： | PLL 時鐘驅動器 |
| PLL： | 帶旁路 |
| 輸入： | CMOS |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 80MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 管件 |
1
PS8382C
11/06/08
ProductPinConfiguration
Logic Block Diagram
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PI6C2502
Product Description
The PI6C2502 features a low-skew, low-jitter, phase-locked loop
(PLL) clock driver. By connecting the feedback FB_OUT output
to the feedback FB_IN input, the propagation delay from the
CLK_IN input to any clock output will be nearly zero.
Product Features
High-PerformancePhase-Locked-LoopClockDistribution
for Networking,
Synchronous DRAM modules for server/workstation/
PC applications
Allows Clock Input to have Spread Spectrum
modulation for EMI reduction
Zero Input-to-Output delay
Lowjitter:Cycle-to-Cyclejitter±100psmax.
On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
Operates at 3.3V VCC
Wide range of Clock Frequencies up to 80 MHz
Package (Pb-Free & Green): Plastic 8-pin SOIC Package (W)
8-Pin
W
Phase-Locked Loop Clock Driver
Application
If a system designer needs more than 16 outputs with the features
just described, using two or more zero-delay buffers such as
PI6C2509Q, and PI6C2510Q, is likely to be impractical. The
device-to-device skew introduced can significantly reduce the
performance. Pericom recommends the use of a zero-delay buffer
and an eighteen output non-zero-delay buffer. As shown in Figure
1, this combination produces a zero-delay buffer with all the signal
characteristics of the original zero-delay buffer, but with as many
outputs as the non-zero-delay buffer part. For example, when
combined with an eighteen output non-zero delay buffer, a system
designer can create a seventeen-output zero-delay buffer.
Figure 1. This Combination Provides Zero-Delay Between the
Reference Clocks Signal and 17 Outputs
CLK_IN
FB_IN
PLL
AVCC
FB_OUT
CLK_OUT
1
2
3
VCC
4
CLK_OUT
CLK_IN
GND
FB_IN
8
7
6
5
AGND
FB_OUT
AVCC
17
Zero Delay
Buffer
PI6C2502
Reference
Clock
Signal
CLK_OUT
Feedback
18 Output
Non-Zero
Delay
Buffer
V
08-0298
相關PDF資料 |
PDF描述 |
|---|---|
| PI6C2504AQE | IC PLL CLOCK DRIVER 4OUT 16-QSOP |
| PI6C2504QE | IC PLL CLOCK DRIVER 4OUT 16-QSOP |
| PI6C2510-133ELE | IC PLL CLOCK DVR 10OUT 24-TSSOP |
| PI6C2510ALE | IC PLL CLOCK DVR 10OUT 24-TSSOP |
| PI6C2972FCE | IC PLL CLOCK DRIVER 52-LQFP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI6C2502WEX | 功能描述:鎖相環(huán) - PLL 3.3v PLL Clock Drivr RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6C2504 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:Phase-Locked Loop Clock Driver with 4 Clock Outputs |
| PI6C2504A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:Phase-Locked Loop Clock Driver with 4 Clock Outputs |
| PI6C2504AQ | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:Phase-Locked Loop Clock Driver with 4 Clock Outputs |
| PI6C2504AQE | 功能描述:鎖相環(huán) - PLL 1:4 Zero Delay Clock Buffer RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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