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參數(shù)資料
| 型號(hào)： | PSD9134V90MT |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| 中文描述： | Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器 |
| 文件頁(yè)數(shù)： | 46/110頁(yè) |
| 文件大小： | 1737K |
| 代理商： | PSD9134V90MT |
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
46/110
80C31
Figure
21
shows the bus interface for the 80C31,
which has an 8-bit multiplexed address/data bus.
The lower address byte is multiplexed with the
data bus. The MCU control signals Program Se-
lect Enable (PSEN, CNTL2), Read Strobe (RD,
CNTL1), and Write Strobe (WR, CNTL0) may be
used for accessing the internal memory and I/O
Ports blocks. Address Strobe (ALE/AS, PD0)
latches the address.
Figure 21. Interfacing the PSD with an 80C31
EA/VP
X1
X2
RESET
RESET
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0(WR)
CNTL1(RD)
CNTL2(PSEN)
PD0-ALE
PD1
PD2
RESET
RD
WR
PSEN
ALE/P
TXD
RXD
RESET
29
28
27
25
24
23
22
21
30
31
32
33
34
35
36
37
39
38
37
36
35
34
33
32
31
19
18
9
12
13
14
15
1
2
3
4
5
6
7
8
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
39
40
41
42
43
44
45
46
47
50
48
49
10
9
8
7
6
5
4
3
2
52
51
PSD
80C31
AD7-AD0
AD[7:0]
21
22
23
24
25
26
27
28
17
16
29
30
A8
A9
A10
A11
A12
A13
A14
A15
RD
WR
PSEN
ALE
11
10
RESET
20
19
18
17
14
13
12
11
AI02880C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD913512JIT | PECL to TTL Clock Driver; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37 |
| PSD913512JT | BBG ECL/TTL CLOCK DRVR; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37 |
| PSD913512MIT | PECL to TTL Clock Driver; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500 |
| PSD913512MT | PECL to TTL Clock Driver; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500 |
| PSD913515JIT | BBG ECL/TTL CLOCK DRVR; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD913512JIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913512JT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913512MIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913512MT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913515JIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
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