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參數(shù)資料
型號： PSD9134V90MT
廠商： 意法半導(dǎo)體
英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述： Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器
文件頁數(shù)： 57/110頁
文件大小： 1737K
代理商： PSD9134V90MT
57/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Table 26. Drive Register Pin Assignment
Note: 1. NA = Not Applicable.
Port Data Registers
The Port Data Registers, shown in Table
27
, are
used by the MCU to write data to or read data from
the ports. Table
27
shows the register name, the
ports having each register type, and MCU access
for each register type. The registers are described
below.
Data In
Port pins are connected directly to the Data In buff-
er. In MCU I/O input mode, the pin input is read
through the Data In buffer.
Data Out Register
Stores output data written by the MCU in the MCU
I/O output mode. The contents of the Register are
driven out to the pins if the Direction Register or
the output enable product term is set to ’1.’ The
contents of the register can also be read back by
the MCU.
Output Macrocells (OMC).
The CPLD Output
Macrocells (OMC) occupy a location in the MCU’s
address space. The MCU can read the output of
the Output Macrocells (OMC). If the OMC Mask
Register bits are not set, writing to the macrocell
loads data to the macrocell flip-flops. See the sec-
tion entitled
PLDS, page 33
.
OMC Mask Register
Each OMC Mask Register bit corresponds to an
Output Macrocell (OMC) flip-flop. When the OMC
Mask Register bit is set to a 1, loading data into the
Output Macrocell (OMC) flip-flop is blocked. The
default value is 0 or unblocked.
Table 27. Port Data Registers
Drive
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port B
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port C
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port D
NA
1
NA
1
NA
1
NA
1
NA
1
Slew
Rate
Slew
Rate
Slew
Rate
Register Name
Port
MCU Access
Data In
A,B,C,D
READ – input on pin
Data Out
A,B,C,D
WRITE/READ
Output Macrocell
A,B,C
READ – outputs of macrocells
WRITE – loading macrocells flip-flop
Mask Macrocell
A,B,C
WRITE/READ – prevents loading into a given
macrocell
Input Macrocell
A,B,C
READ – outputs of the Input Macrocells
Enable Out
A,B,C
READ – the output enable control of the port driver
相關(guān)PDF資料
PDF描述
PSD913512JIT PECL to TTL Clock Driver; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD913512JIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913512JT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913512MIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913512MT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913515JIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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