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參數資料
型號： PSD9134V90MT
廠商： 意法半導體
英文描述： Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述： Flash在系統可編程ISP的外設的8位微控制器
文件頁數： 99/110頁
文件大小： 1737K
代理商： PSD9134V90MT
99/110
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Table 70. ISC Timing (3V devices)
Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For Program or Erase PLD only.
Table 71. Power-down Timing (5V devices)
Note: 1. t
CLCL
is the period of CLKIN (PD1).
Table 72. Power-down Timing (3V devices)
Note: 1. t
CLCL
is the period of CLKIN (PD1).
Symbol
Parameter
Conditions
-12
-15
-20
Unit
Min
Max
Min
Max
Min
Max
t
ISCCF
Clock (TCK, PC1) Frequency (except for
PLD)
(Note
1
)
12
10
9
MHz
t
ISCCH
Clock (TCK, PC1) High Time (except for
PLD)
(Note
1
)
40
45
51
ns
t
ISCCL
Clock (TCK, PC1) Low Time (except for
PLD)
(Note
1
)
40
45
51
ns
t
ISCCFP
Clock (TCK, PC1) Frequency (PLD only)
(Note
2
)
2
2
2
MHz
t
ISCCHP
Clock (TCK, PC1) High Time (PLD only)
(Note
2
)
240
240
240
ns
t
ISCCLP
Clock (TCK, PC1) Low Time (PLD only)
(Note
2
)
240
240
240
ns
t
ISCPSU
ISC Port Set Up Time
12
13
15
ns
t
ISCPH
ISC Port Hold Up Time
5
5
5
ns
t
ISCPCO
ISC Port Clock to Output
30
36
40
ns
t
ISCPZV
ISC Port High-Impedance to Valid Output
30
36
40
ns
t
ISCPVZ
ISC Port Valid Output to
High-Impedance
30
36
40
ns
Symbol
Parameter
Conditions
-70
-90
-15
Unit
Min
Max
Min
Max
Min
Max
t
LVDV
ALE Access Time from Power-down
80
90
150
ns
t
CLWH
Maximum Delay from
APD Enable to Internal PDN Valid
Signal
Using CLKIN
(PD1)
15 * t
CLCL1
μs
Symbol
Parameter
Conditions
-12
-15
-20
Unit
Min
Max
Min
Max
Min
Max
t
LVDV
ALE Access Time from Power-down
145
150
200
ns
t
CLWH
Maximum Delay from APD Enable to
Internal PDN Valid Signal
Using CLKIN
(PD1)
15 * t
CLCL1
μs
相關PDF資料
PDF描述
PSD913512JIT PECL to TTL Clock Driver; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37
PSD913512JT BBG ECL/TTL CLOCK DRVR; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37
PSD913512MIT PECL to TTL Clock Driver; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500
PSD913512MT PECL to TTL Clock Driver; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500
PSD913515JIT BBG ECL/TTL CLOCK DRVR; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37
相關代理商/技術參數
參數描述
PSD913512JIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913512JT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913512MIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913512MT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913515JIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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