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參數(shù)資料
| 型號： | PSD913515JIT |
| 廠商： | 意法半導體 |
| 英文描述： | BBG ECL/TTL CLOCK DRVR; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37 |
| 中文描述： | Flash在系統(tǒng)可編程ISP的外設(shè)的8位微控制器 |
| 文件頁數(shù)： | 72/110頁 |
| 文件大小： | 1737K |
| 代理商： | PSD913515JIT |
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
72/110
AC/DC PARAMETERS
These tables describe the AD and DC parameters
of the PSD:
DC Electrical Specification
AC Timing Specification
PLD Timing
–
Combinatorial Timing
–
Synchronous Clock Mode
–
Asynchronous Clock Mode
–
Input Macrocell Timing
MCU Timing
–
READ Timing
–
WRITE Timing
–
Peripheral Mode Timing
■
■
–
Power-down and Reset Timing
The following are issues concerning the parame-
ters presented:
–
In the DC specification the supply current is
given for different modes of operation. Before
calculating the total power consumption,
determine the percentage of time that the PSD
is in each mode. Also, the supply power is
considerably different if the Turbo Bit is ’0.’
–
The AC power component gives the PLD,
Flash memory, and SRAM mA/MHz
specification. Figures
35
and
36
show the PLD
mA/MHz as a function of the number of
Product Terms (PT) used.
–
In the PLD timing parameters, add the
required delay when Turbo Bit is ’0.’
Figure 35. PLD I
CC
/Frequency Consumption (5V range)
110
Figure 36. PLD I
CC
/Frequency Consumption (3V range)
0
10
20
30
40
60
70
80
90
100
V
CC
= 5V
TURBO ON (100%)
50
0
10
15
5
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
I
C
TURBO ON (25%)
TURBOOFF
TURBO OFF
PT 100%
PT 25%
AI02894
0
10
20
30
40
50
60
V
CC
= 3V
0
10
15
5
20
25
I
C
TURBO ON (100%)
TURBO ON (25%)
TURBOOFF
TURBO OFF
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
PT 100%
PT 25%
AI03100
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD913515JT | 1:9 Clock Driver; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500 |
| PSD913515MIT | BBG ECL/TTL CLOCK DRVR; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500 |
| PSD913515MT | BBG ECL/TTL CLOCK DRVR; Package: 28 LEAD PLCC; No of Pins: 28; Container: Rail; Qty per Container: 37 |
| PSD913520JIT | ECL/TTL Clock Driver; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500 |
| PSD913520JT | BBG ECL/TTL CLOCK DRVR; Package: 28 LEAD PLCC; No of Pins: 28; Container: Tape and Reel; Qty per Container: 500 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD913515JT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913515MIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913515MT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913520JIT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913520JT | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
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