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參數資料
| 型號： | Q6701-H6481 |
| 廠商： | SIEMENS AG |
| 英文描述： | Quadruple Transceiver for S/T Interface QUAT-S |
| 中文描述： | 四聯收發器的S / T接口葛- ? |
| 文件頁數： | 37/72頁 |
| 文件大小： | 1267K |
| 代理商： | Q6701-H6481 |
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PEB 2084
Semiconductor Group
37
The codes (C/I = 1100
H
and 1100
H
) can only be used when the QUAT-S is in the state
G3 activated (during INFO 4 transmission). Refer to
chapter 3.6.
For a detailed description of the D-Channel Arbiter refer to “ELIC, PEB 20550, Technical
Manual 9.93”, page 54, chapter 2.2.8.
D-Channel Access According to CCITT I.430 (Star Configuration)
The D-channel access is arbitrated among the terminals themselves,
if the QUAT-S Auxiliary Register is programmed to DCM(1:0) = 10.
Figure 20
QUAT-S in LT-S Mode Supporting Arbitration According to CCITT I.430
The D-channel access control is established as a logical passive bus structure. All
received D-channels are ANDed and the resulting value (internally connected to the pin
CEB) is sent back as Echo bit on all involved S/T interfaces.
If more QUAT-S work in parallel the CEB pins (open drain output) are wired via an
external pull-up resistor to
V
DD
.
The “short passive bus”, a system of multiple TE’s accessing a single D-channel, is
extended to multiple physical S lines still representing a single logical “short passive
bus”. It is a system with multiple B-channels using a single D-channel.
Only the winning D-channel reaches the ELIC. The other D-channels remain blocked
until a TE encounters 8 (10) E-bits equal to the D-bit in a row.
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