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參數(shù)資料
| 型號(hào)： | Q67100-Q1143 |
| 廠商： | SIEMENS AG |
| 英文描述： | 3.3V 4M x 4-Bit EDO-Dynamic RAM |
| 中文描述： | 3.3 4米× 4位江戶動(dòng)態(tài)隨機(jī)存儲(chǔ)器 |
| 文件頁數(shù)： | 1/53頁 |
| 文件大小： | 418K |
| 代理商： | Q67100-Q1143 |
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HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Data Book
1
12.99
The HYB 39S64400/800/160BT are four bank Synchronous DRAM’s organized as
4 banks
×
4MBit
×
4, 4 banks
×
2 MBit
×
8 and 4 banks
×
1 Mbit
×
16 respectively. These synchron-
ous devices achieve high speed data transfer rates by employing a chip architecture that prefects
multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using
the Infineon advanced 0.2
μ
m 64 MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for Synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rates than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3 V
±
0.3 V power supply and are available in TSOPII packages.
High Performance:
Fully Synchronous to Positive Clock Edge
0 to 70
°
C operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length: 1, 2, 4, 8
Full page (optional) for sequential wrap
around
Multiple Burst Read with Single Write
Operation
Automatic and Controlled Precharge
Command
Data Mask for Read/Write Control (x4, x8)
Data Mask for Byte Control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
4096 Refresh Cycles / 64 ms
Random Column Address every CLK
(1-N Rule)
Single 3.3 V
±
0.3 V Power Supply
LVTTL Interface
Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
-7.5 version for PC133 3-3-3 application
-8 version for PC100 2-2-2 applications
-7.5
-8
Units
f
CKMAX
133
125
MHz
t
CK3
7.5
8
ns
t
AC3
5.4
6
ns
t
CK2
10
10
ns
t
AC2
6
6
ns
64-MBit Synchronous DRAM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Q67100-Q1144 | 3.3V 4M x 4-Bit EDO-Dynamic RAM |
| Q67100-Q1147 | 2M x 8-Bit Dynamic RAM |
| Q67100-Q1148 | 2M x 8-Bit Dynamic RAM |
| Q67100-Q1151 | 2M x 8 - Bit Dynamic RAM 2k Refresh |
| Q67100-Q1152 | 2M x 8 - Bit Dynamic RAM 2k Refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Q67100-Q1144 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3V 4M x 4-Bit EDO-Dynamic RAM |
| Q67100-Q1147 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2M x 8-Bit Dynamic RAM |
| Q67100-Q1148 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2M x 8-Bit Dynamic RAM |
| Q67100-Q1151 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2M x 8 - Bit Dynamic RAM 2k Refresh |
| Q67100-Q1152 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2M x 8 - Bit Dynamic RAM 2k Refresh |
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