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參數資料
| 型號： | romr0002 |
| 廠商： | SIEMENS AG |
| 英文描述： | MultiMediaCard R0002 2 Mbyte ROM(多媒體卡 R0002 2 Mbyte ROM) |
| 中文描述： | 多媒體R0002 2字節的光盤（多媒體卡R0002 2字節光盤） |
| 文件頁數： | 38/41頁 |
| 文件大小： | 207K |
| 代理商： | ROMR0002 |
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Siemens
Product Manual R0002
Semiconductor Group
38
3.1
At a reduced clock rate the card can drive a load of up to 30 cards:
With this load capacity the operating frequency is reduced to 5MHz.
The access time (t
AT
) is divided into two parts:
T
SAD
: The synchronous access time. This time defines the time of the maximum number of
cycles which are required to access a byte of the memory field.
T
AAD
: The asynchronous access time to read a byte out of the memory field
The synchronous part of the access time is seven cycles. At 20 MHz one cycle is 50 ns (1/f
CLK
),
multiplied with N
SAD
the resulting frame time is
T
SAD
=0.35
μ
s. The asynchronous access delay of
the R0002 is
T
AAD
=0.6
μ
s maximum. The resulting memory access time t
AT
is equal to the sum of
both parts:
Low-Level Output Voltage
(open drain mode)
V
OL
0.3V
V
at I
OLMIN
Command Input: CMD
(Related to CLK)
Input setup time
Input hold time
t
ISU
t
IH
3
3
ns
ns
S. Figure 20
S. Figure 20
Outputs: CMD, DAT
(Related to CLK)
Output setup time
Hold time
t
OSU
t
OH
5
5
ns
ns
S. Figure 20
S. Figure 20
Parameter
Symbol
Min
Max
Unit
Remark
Table 30: Operating characteristics
C
L
30
n C
catd
C
bus
+
30 7
pF
40
pF
+
250
pF
=
=
=
V
IL
V
IH
V
IL
V
OH
V
OL
V
IH
Clock
Input
Output
Figure 20: Timing Diagram of Data Input and Output
PP
t
WL
t
WH
t
ISU
t
IH
t
OH
t
HL
t
LH
valid
valid
valid
valid
t
OSU
t
AT
T
AAD
T
SAD
+
=
with
T
SAD
N
CLK
-f
=
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