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參數(shù)資料
| 型號： | rosa51 |
| 廠商： | SIEMENS AG |
| 英文描述： | MultiMediaCard Adapter(多媒體卡適配器) |
| 中文描述： | 多媒體卡（多媒體卡適配器） |
| 文件頁數(shù)： | 28/54頁 |
| 文件大小： | 510K |
| 代理商： | ROSA51 |
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Siemens AG Semiconductors
Version 5.2
Confidential
20/10/1998
28
This process generates a mmcclk enable signal always one cycle before the rising edge of clk_out.
Most processes in rosa_if are sensitive to mmcclk only!
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The adapter interface unit connects the application with the ROSA controller. It implements a simple
byte parallel interface with four control lines and an optional interrupt signal. Since this interface
may be asynchronous all inputs are latched in. All outputs going to the application are high-Z as
long as the chip select signal is deasserted. When ROSA is selected the interface waits for the
beginning of a transfer. When STB_N is asserted strobe, control/data and read/write are propagated
to rosa_rc and rosa_mc; except a read of the control register. This register reflects the general sta-
tus of ROSA and must always be accessible without interfering with any of the controllers in ROSA.
To acknowledge the transaction either the central controller rosa_rc or when transferring data
rosa_mc must send their acknowledge signal. On writes data is taken from the bus when ACK_N is
asserted. On reads data is first latched in a data_reg before in can be put on the bus.
The interrupt controller (rosa_irq) is a subunit of rosa_ad.
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rcif_speed[6:0]
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These lines reflect the maximum MultiMediaCard clock speed entry of the
CSD. It has always the value of the slowest card in the stack.
These lines reflect the read / write speed ratio entry in the CSD.
This signal selects the identification mode or data transfer mode speed.
These lines select the read or write speed.
These lines reflect the configuration register defining the clock ratio
between ROSA clk and a 20 MHz clock.
This signal enables dummy clk_out cycle generation. It is active high.
rosa_cmd requests clk_out cycle generation. It is active high.
rosa_mc requests clk_out cycle generation. It is active high.
This signal indicates a rising edge on the MultiMediaCard bus
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line. It
is active high.
This signal is connected to the MultiMediaCard bus
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line.
rcif_swfactor[2:0]
rcif_rod_out
mcif_datrw[1:0]
rcif_clkperiod[2:0]
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rcif_clken
if_cmdclken
mcif_datclken
mmcclk
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clk_out
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