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參數資料
| 型號： | S2054 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 網絡接口 |
| 英文描述： | Fibre Channel and GigaBit Ethernet Transceiver(帶雙接收和發送串行I/O的光纖通道和千兆位以太網收發器) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-64 |
| 文件頁數： | 1/15頁 |
| 文件大小： | 306K |
| 代理商： | S2054 |
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
S2054
S2054
March 21, 2001 / Revision A
1
DEVICE
SPECIFICATION
FEATURES
Functionally compliant with ANSI X3T11 Fibre
Channel physical and transmission protocol
standards and IEEE 802.3z Gigabit Ethernet
Applications
Transmitter incorporates phase-locked loop
(PLL) providing clock synthesis from low-speed
differential LVPECL or LVTTL reference
Receiver PLL configured for clock and data
recovery
1250 and 1062 Mb/s operation
10-bit parallel LVTTL compatible interface
1.1mW typical power dissipation
+3.3V power supply
Low-jitter serial LVPECL compatible interface
Lock detect
Dual serial inputs and outputs
Local loopback
Compact 10mm x 10mm 64 PQFP package
Fibre Channel framing performed by receiver
Continuous downstream clocking from receiver
Low jitter LVPECL reference clock input option
APPLICATIONS
High-speed data communications
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
RAID drives
Mass storage devices
GENERAL DESCRIPTION
The S2054 transmitter and receiver chip is designed
to perform high-speed serial data transmission over
fiber optic or coaxial cable interfaces conforming to
the requirements of the ANSI X3T11 Fibre Channel
specification and IEEE 802.3z Gigabit Ethernet. The
chip runs at 1250.0, and 1062.5 Mbit/s data rates
with associated 10-bit data word.
The S2054 is similar to the S2052. The S2054 pro-
vides dual transmit and receive serial I/O in addition
to an optional LVTTL or differential LVPECL refer-
ence clock input and high drive LVTTL outputs. The
dual transmit and receive serial I/O are useful for
backbone applications in which redundant optical or
electrical links are required. The differential LVPECL
reference clock provides the lowest transmitter output
jitter solution. The high drive LVTTL outputs allow
longer trace lengths or connectors to be used be-
tween the S2054 and the Media Access Controller.
The chip performs parallel-to-serial and serial-to-paral-
lel conversion and framing for block-encoded data. The
transmitter’s on-chip PLL synthesizes the high-speed
clock from a low-speed reference. The receiver’s on-
chip PLL synchronizes directly to incoming digital signal
to receive the data stream. The transmitter and re-
ceiver each support differential LVPECL-compatible I/
O for fiber optic component interfaces, to minimize
crosstalk and maximize data integrity. Local line
loopback mode is provided for system diagnostics. Dual
serial inputs and dual serial outputs facilitate redun-
dant design and provide maximum flexibility.
Figure 1 shows a typical configuration incorporating
the chip, which is compatible with AMCC’s S2036 Open
Fiber Control (OFC) device (for 1062 operation only).
Figure 1. System Block Diagram
Optical
TX
Optical
RX
Optical
RX
Optical
TX
S2036
Open Fiber
Control
(OFC)
S2036
Open Fiber
Control
(OFC)
S2054
S2054
Gigabit
Ethernet
Controller
Gigabit
Ethernet
Controller
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| S2055A | SILICON DIFFUSED POWER TRANSISTOR |
| S2057 | Port Bypass Circuit for Fibre Channel and GigaBit Ethernet(用于光纖通道和千兆位以太網的端口旁路電路) |
| S2058 | Port Bypass and Repeater for Fibre Channel Arbitrated Loop(用于光纖通道仲裁環路的端口旁路電路和中繼器) |
| S2060 | GIGABIT ETHERNET TRANSCEIVER |
| S2060A | GIGABIT ETHERNET TRANSCEIVER |
相關代理商/技術參數 |
參數描述 |
|---|---|
| S2054AG4 | 制造商:TYAN 功能描述:M-ATX SOCKET-370 INTEL 810 - Bulk |
| S2055 | 制造商:ISC 制造商全稱:Inchange Semiconductor Company Limited 功能描述:Silicon NPN Power Transistors |
| S2055A | 制造商:SAVANTIC 制造商全稱:Savantic, Inc. 功能描述:Silicon NPN Power Transistors |
| S2055AF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SILICON DIFFUSED POWER TRANSISTOR |
| S2055F | 制造商:ISC 制造商全稱:Inchange Semiconductor Company Limited 功能描述:Silicon NPN Power Transistors |
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