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參數資料
| 型號： | S29CD032J1JFAI122 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 1M X 32 FLASH 2.7V PROM, 54 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80 |
| 文件頁數： | 17/78頁 |
| 文件大小： | 1825K |
| 代理商： | S29CD032J1JFAI122 |
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22
S29CD-J & S29CL-J Flash Family
S29CD-J_CL-J_00_B1 September27,2006
Prel imi n ary
8.3
Hardware Reset (RESET#)
The RESET# pin is an active low signal that is used to reset the device under any circumstances.
A logic “0” on this input forces the device out of any mode that is currently executing back to the
reset state. RESET# may be tied to the system reset circuitry. A system reset would thus also
reset the device. To avoid a potential bus contention during a system reset, the device is isolated
from the DQ data bus by tristating the data outputs for the duration of the RESET pulse. All data
outputs are “don’t care” during the reset operation.
If RESET# is asserted during a program or erase operation, the RY/BY# output remains low until
the reset operation is internally complete. The RY/BY# pin can be used to determine when the
reset operation is complete. Since the device offers simultaneous read/write operation, the host
system may read a bank after a period of tREADY2, if the bank was in the read/reset mode at the
time RESET# was asserted. If one of the banks was in the middle of either a program or erase
operation when RESET# was asserted, the user must wait a period of tREADY before accessing
that bank.
Asserting RESET# during a program or erase operation leaves erroneous data stored in the ad-
dress locations being operated on at the time of device reset. These locations need updating after
the reset operation is complete. See Section 18.4 for timing specifications.
Asserting RESET# active during VCC and VIO power-up is required to guarantee proper device
8.4
Synchronous (Burst) Read Mode & Configuration Register
When a series of adjacent addresses need to be read from the device, the synchronous (or burst
read) mode can be used to significantly reduce the overall time needed for the device to output
array data. After an initial access time required for the data from the first address location, sub-
sequent data is output synchronized to a clock input provided by the system.
The device offers a linear method of burst read operation which is discussed in 2-, 4-, 8- Double
Since the device defaults to asynchronous read mode after power-up or a hardware reset, the
configuration register must be set in order to enable the burst read mode. Other Configuration
Register settings include the number of wait states to insert before the initial word (tIACC) of each
burst access and when RDY indicates that data is ready to be read. Prior to entering the burst
mode, the system first determines the configuration register settings (and read the current reg-
ister settings if desired via the Read Configuration Register command sequence), then write the
configuration register command sequence. See Configuration Register on page 26, and
Table 20.1, Memory Array Command Definitions (x32 Mode), on page 71 for further details.
Once the configuration register is written to enable burst mode operation, all subsequent reads
from the array are returned using the burst mode protocols.
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