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參數資料
| 型號： | S29CL016J1JFFM112 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 512K X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80 |
| 文件頁數： | 22/78頁 |
| 文件大小： | 1825K |
| 代理商： | S29CL016J1JFFM112 |
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September 27, 2006 S29CD-J_CL-J_00_B1
S29CD-J & S29CL-J Flash Family
27
Pr el im i n a r y
Table 8.5 describes the Configuration Register settings.
8.5
Autoselect
The autoselect mode provides manufacturer and device identification, and sector protection ver-
ification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for
programming equipment to automatically match a device to be programmed with its correspond-
ing programming algorithm. However, the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect mode requires VID on address pin A9. Ad-
dress pins A6, A1, and A0 must be as shown in Table 8.7. In addition, when verifying sector pro-
tection, the sector address must appear on the appropriate highest order address bits. Table 8.7
Table 8.5 Configuration Register
Configuration Register
CR15 = Read Mode (RM)
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
CR14 = Reserved for Future Enhancements
These bits are reserved for future use. Set these bits to 0.
CR13–CR10 = Initial Burst Access Delay Configuration (IAD3-IAD0)
0000 = 2 CLK cycle initial burst access delay
0001 = 3 CLK cycle initial burst access delay
0010 = 4 CLK cycle initial burst access delay
0011 = 5 CLK cycle initial burst access delay
0100 = 6 CLK cycle initial burst access delay
0101 = 7 CLK cycle initial burst access delay
0110 = 8 CLK cycle initial burst access delay
0111 = 9 CLK cycle initial burst access delay—Default
CR9 = Data Output Configuration (DOC)
0 = Hold Data for 1-CLK cycle—Default
1 = Reserved
CR8 = IND/WAIT# Configuration (WC)
0 = IND/WAIT# Asserted During Delay—Default
1 = IND/WAIT# Asserted One Data Cycle Before Delay
CR7 = Burst Sequence (BS)
0 = Reserved
1 = Linear Burst Order—Default
CR6 = Clock Configuration (CC)
0 = Reserved
1 = Burst Starts and Data Output on Rising Clock Edge—Default
CR5–CR3 = Reserved For Future Enhancements (R)
These bits are reserved for future use. Set these bits to 0.
CR2–CR0 = Burst Length (BL2–BL0)
000 = Reserved, burst accesses disabled (asynchronous reads only)
001 = 64 bit (8-byte) Burst Data Transfer - x32 Linear
010 = 128 bit (16-byte) Burst Data Transfer - x32 Linear
011 = 256 bit (32-byte) Burst Data Transfer - x32 Linear (device default)
100 = Reserved, burst accesses disabled (asynchronous reads only)
101 = Reserved, burst accesses disabled (asynchronous reads only)
110 = Reserved, burst accesses disabled (asynchronous reads only)
Table 8.6 Configuration Register After Device Reset
CR15
CR14
CR13
CR12
CR11
CR10
CR9
CR8
RM
Reserve
IAD3
IAD2
IAD1
IAD0
DOC
Reserve
1
0011
1
0
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
BS
CC
Reserve
BL2
BL1
BL0
1
1000
1
0
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