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參數資料
| 型號： | S29CL032J0RFAI113 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80 |
| 文件頁數： | 20/78頁 |
| 文件大小： | 1825K |
| 代理商： | S29CL032J0RFAI113 |
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September 27, 2006 S29CD-J_CL-J_00_B1
S29CD-J & S29CL-J Flash Family
25
Pr el im i n a r y
Note: Operation is shown for the 32-bit data bus. Figure shown with 3-CLK initial access delay configuration, linear address,
4-doubleword burst, output on rising CLD edge, data hold for 1-CLK, IND/WAIT# asserted on the last transfer before wrap-
around.
Figure 8.3 End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation
8.4.2
Initial Burst Access Delay
Initial Burst Access Delay is defined as the number of clock cycles that must elapse from the first
valid clock edge after ADV# assertion (or the rising edge of ADV#) until the first valid CLK edge
when the data is valid. Burst access is initiated and the address is latched on the first rising CLK
edge when ADV# is active or upon a rising ADV# edge, whichever comes first. The Initial Burst
Access Delay is determined in the Configuration Register (CR13-CR10). Refer to Table 8.5 for the
initial access delay configurations under CR13-CR10. See Figure 8.4 for the Initial Burst Delay
Control timing diagram. Note that the Initial Access Delay for a burst access has no effect on
asynchronous read operations.
Table 8.4 Burst Initial Access Delay
CR13
CR12
CR11
CR10
Initial Burst Access (CLK cycles)
000
1
3
001
0
4
001
1
5
010
0
6
010
1
7
0
1
0
8
011
1
9
CE#
CLK
ADV#
Addresses
OE#
Data
Address 1
Address 2
Invalid
D1
D2
D3
D0
Address 1 Latched
3 Clock Delay
IND/WAIT#
VIL
VIH
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