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參數(shù)資料
| 型號： | S29CL032J0RFAN130 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, FORTIFIED, BGA-80 |
| 文件頁數(shù)： | 64/78頁 |
| 文件大小： | 1825K |
| 代理商： | S29CL032J0RFAN130 |
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September 27, 2006 S29CD-J_CL-J_00_B1
S29CD-J & S29CL-J Flash Family
65
Pr el im i n a r y
Notes:
1. The timings are similar to synchronous read timings and asynchronous data polling Timings/Toggle bit Timing.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is
complete, the toggle bits will stop toggling.
3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is
active one clock cycle before data.
4. Data polling requires burst access time delay.
Figure 18.14 Synchronous Data Polling Timing/Toggle Bit Timings
* Valid address for sector protect: A[7:0] = 3Ah. Valid address for sector unprotect: A[7:0] = 3Ah.
** Command for sector protect is 68h. Command for sector unprotect is 60h.
*** Command for sector protect verify is 48h. Command for sector unprotect verify is 40h.
Figure 18.15 Sector Protect/Unprotect Timing Diagram
CE#
CLK
AVD#
Addresses
OE#
Data
RDY
Status Data
VA
tOE
Sector Protect: 150 s
Sector Unprotect: 15 ms
1 s
RESET#
SA, A6,
A1, A0
Data
CE#
WE#
OE#
60h
60h/68h**
40h/48h***
Valid*
Status
Sector Protect/Unprotect
Verify
VIH
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| S29CL032J0RFFI110 | 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80 |
| S29CL032J0RFFN130 | 1M X 32 FLASH 3.3V PROM, 48 ns, PBGA80 |
| S29CL032J1JFAI110 | 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| S29CL032J1MFAN120 | 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| S29CL032J0PQAN102 | 1M X 32 FLASH 3.3V PROM, 54 ns, PQFP80 |
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