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參數資料
| 型號： | S4402 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | BiCMOS PLL Clock Generator(能產生6個時鐘輸出的BiCMOS鎖相環時鐘發生器) |
| 中文描述： | BiCMOS工藝PLL時鐘發生器（能產生6個時鐘輸出的BiCMOS工藝鎖相環時鐘發生器） |
| 文件頁數： | 1/13頁 |
| 文件大小： | 154K |
| 代理商： | S4402 |
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
Page 1
S4402/S4403
BiCMOS PLL CLOCK GENERATORS
FEATURES
Generates six clock outputs from 20 MHz to
80 MHz (the S4403 generates ten outputs and
HFOUT generates 10MHz to 40MHz)
21 selectable phase/frequency relationships for
the clock outputs
Compensates for clock skew by allowing output
delay adjustment down to 3.125 ns increments
TTL outputs have less than 400 ps maximum
skew
Lock Detect output indicates loop status
Internal PLL with VCO operating at 160 to
320 MHz
Test Enable input allows VCO bypass for open-
loop operation in board test
Maximum 1.0 ns of phase error (750 ps from
part to part)
Proven 1.0 micron BiCMOS technology
Single +5V power supply operation
28/44 PLCC packages
APPLICATIONS
CMOS ASIC Systems
High-speed Microprocessor Systems
Backplane Clock Deskew and Distribution
GENERAL DESCRIPTION
The S4402/S4403 BiCMOS clock generators allow
the user to generate multiphase TTL clocks in the
10–80 MHz range with less than 400 ps of skew. Use
of a single off-chip filter allows an entire 160–320
MHz phase-locked loop (PLL) to be implemented on-
chip. Divide-by-two and times-two outputs allow the
ability to generate output clocks at half, equal to, or
twice the reference clock input frequency. By using
the programmable divider and phase selector, the
user can select from up to 21 different output rela-
tionships. The outputs can be phase-adjusted in in-
crements as small as 3.125 ns to tailor the clocks to
exact system requirements.
Implemented in AMCC’s proven 1.0 micron BiCMOS
technology, the S4402 generates six TTL outputs,
while the S4403 provides those six plus four dupli-
cates (FOUT0A–FOUT3A) for a total of ten. Output
enables are provided for the various banks, allowing
clock control for board and system tests.
Figure 1. Clock Generator Block Diagram
PHASE
DETECTOR
CHARGE
PUMP
VCO
I
0
I
1
MUX
SELECT
REFCLK
FBCLK
TSTEN
DIVSEL
PHSEL0
PHSEL1
RESET
OUTEN0
OUTEN1
DIVIDER
AND
PHASE
CONTROL
LOGIC
HFOUT
X2FOUT
FOUT0
FOUT1
FOUT2
FOUT3
FOUT0A
FOUT1A
FOUT2A
FOUT3A
OUTEN2
LOCK
FILTER
Digital
+5V
0V
Analog
+5V
0V
NOTE: FOUT0A, FOUT1A,
FOUT2A, FOUT3A, and
OUTEN2 apply only to the
S4403.
÷ 2
DEVICE SPECIFICATION
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