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參數(shù)資料
| 型號： | SC402BMLTRT |
| 廠商： | Semtech |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 1425K |
| 描述： | IC REG DL BCK/LINEAR SYNC 32MLPQ |
| 標準包裝： | 1 |
| 系列： | EcoSpeed®, SmartDrive™ |
| 拓撲： | 降壓（降壓）同步（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開關： | 1MHz |
| 電壓/電流 - 輸出 1： | 可調(diào)至 0.6V，10A |
| 電壓/電流 - 輸出 2： | 可調(diào)至 0.75V，200mA |
| 帶 LED 驅動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 是 |
| 電源電壓： | 3 V ~ 28 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-MLPQ（5x5） |
| 包裝： | 標準包裝 |
| 其它名稱： | SC402BMLDKR |
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SC402B
21
LDO Regulator
SC402B has an option to bias the switcher by using an
internal LDO from V
IN
. The LDO output is connected to
VDD internally. The output of the LDO is programmable
by using external resistors from the VDD pin to AGND (see
Figure 9). The feedback pin (FBL) for the LDO is regulated
to 750mV.
Figure 9 LDO Output Voltage Selection
The LDO output voltage is set by the following equation.
2
LDO
1
LDO
R
R
1
mV
750
VLDO
A minimum capacitance of 1糉 referenced to AGND is
normally required at the output of the LDO for stability.
Note that if the LDO voltage is set lower than 4.5V, the
minimum output capacitance for the LDO is 10uF.
LDO ENL Functions
The ENL input is used to enable/disable the internal LDO.
When ENL is a logic low, the LDO is off. When ENL is above
the V
IN
UVLO threshold, the LDO is enabled and the switcher
is also enabled if the EN/PSV and VDD are above their
threshold. The table below summarizes the function of ENL
and EN/PSV pins.
EN/PSV
ENL
LDO Switcher
Disabled Low, < 0.4V OFF OFF
Enabled Low, < 0.4V OFF ON
Disabled 1.0V < High < 2.6V ON OFF
Enabled 1.0V < High < 2.6V ON OFF
Disabled High, > 2.6V ON OFF
Enabled High, > 2.6V ON ON
The ENL pin also acts as the switcher under-voltage lockout
for the V
IN
supply. When SC402B is self-biased from the LDO
and runs from the V
IN
power source only, the V
IN
UVLO
feature can be used to prevent false UV faults for the PWM
output by programming with a resistor divider at the VIN,
ENL and AGND pins. When SC402B has an external bias
voltage at VDD and the ENL pin is used to program the V
IN
UVLO feature, the voltage at FBL needs to be higher than
750mV to force the LDO off.
Timing is important when driving ENL with logic and not
implementing V
IN
UVLO. The ENL pin must transition from
high to low within 2 switching cycles to avoid the PWM
output turning off. If ENL goes below the VIN UVLO
threshold and stays above 1V, then the switcher will turn
off but the LDO will remain on.
LDO Start-up
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
ENL pin
V
IN
input voltage
When the ENL pin is high and V
IN
is above the UVLO point,
the LDO will begin start-up. During the initial phase, when
the V
DD
voltage (which is the LDO output voltage) is less
than 0.75V, the LDO initiates a current-limited start-up
(typically 65mA) to charge the output capacitors while
protecting from a short circuit event. When V
DD
is greater
than 0.75V but still less than 90% of its final value (as
sensed at the FBL pin), the LDO current limit is increased
to ~115mA. When V
DD
has reached 90% of the final value
(as sensed at the FBL pin), the LDO current limit is increased
to ~200mA and the LDO output is quickly driven to the
nominal value by the internal LDO regulator. It is recom-
mended that during LDO start-up to hold the PWM
switching off until the LDO has reached 90% of the final
value. This prevents overloading the current-limited LDO
output during the LDO start-up.
1.
2.
Applications Information (continued)
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