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參數資料
| 型號： | SG6932SZ |
| 廠商： | Fairchild Semiconductor |
| 文件頁數： | 16/20頁 |
| 文件大小： | 919K |
| 描述： | IC PFC CONTROLLER CCM 16SOP |
| 標準包裝： | 2,500 |
| 模式： | 連續導電（CCM） |
| 頻率 - 開關： | 65kHz |
| 電流 - 啟動： | 10µA |
| 電源電壓： | 14 V ~ 20 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
?2007 Fairchild Semiconductor Corporation
www.fairchildsemi.com
SG6932 " Rev. 1.1.3
16
PCB Layout
SG6932 has a single ground pin, which prevents high
sink currents in the output being returned separately.
Good high-frequency or RF layout practices should be
followed. Avoid long PCB traces and component leads.
Locate decoupling capacitors near the SG6932. A
resistor (5 ~ 20? is recommended, connected in
series from the output to the gate of the MOSFET.
Isolating the interference between the PFC and PWM
stages is also important. Figure 32 shows an example
of the PCB layout. The ground trace 1 is connected
from the ground pin to the decoupling capacitor, which
should be low impedance and as short as possible. The
ground trace 2 provides a signal ground and should be
connected directly to the decoupling capacitor C
DD
and/or to the ground pin. The ground trace 3 is
independently tied from the decoupling capacitor to the
PFC output capacitor C
O
.
The ground in the output capacitor C
O
is the major
ground reference for power switching. To provide a
good ground reference and reduce the switching noise
of both the PFC and PWM stages, the ground traces 6
and 7 should be located very near and be low
impedance.
The IPFC pin is connected directly to R
S
through R
3
to
improve noise immunity. Do not incorrectly connect
to the ground trace 2. The IMP and ISENSE pins
should also be connected directly via the resistors R
2
and R
P
to another terminal of R
S
.
Figure 32. PCB Layout
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