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參數(shù)資料
| 型號(hào)： | SI3500-A-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 6/18頁 |
| 文件大小： | 192K |
| 描述： | IC POE SWITCH PWR OVER LAN 20QFN |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 類型： | 以太網(wǎng)供電開關(guān)（PoE） |
| 應(yīng)用： | IP 電話，LAN 網(wǎng)絡(luò)供電，網(wǎng)絡(luò)路由器和交換機(jī) |
| 內(nèi)部開關(guān)： | 是 |
| 電流限制： | 525mA |
| 電源電壓： | 42 V ~ 57 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN（5x5） |
| 包裝： | 管件 |
| 配用： | SMARTPSE24-KIT-ND - KIT EVAL REF 24PORT SPI/UART SI3480MS8-KIT-ND - KIT EVAL 8PORT SI3480/52/SI3500 |
| 其它名稱： | 336-1844-5 |
Si3500
6
Rev. 1.1
Table 5. Electrical Characteristics
Parameter
Description
Min
Typ
Max
Unit
Current Limit
1
Inrush
140
mA
Operating
400
525
mA
Hotswap FET On-Resistance +
R
SENSE
0.5
1.5
W
Switcher Frequency
350
kHz
Maximum Switcher Duty Cycle
ISOSSFT connected to
VDD
50
%
Switching FET On-Resistance
0.3
0.86
W
Regulated Feedback @ pin FB
2
DC Avg.
1.23
V
Regulated Output Voltage Tolerance
2
Output voltage tolerance
@ VOUT
5
5
%
VDD accuracy @ 0.8 mA
42 V <
VPOS <
57 V
4.5
5.5
V
Softstart charging current
Non-isolated
25
礎(chǔ)
Isolated
13
礎(chǔ)
Thermal Shutdown
Junction temperature
160
癈
Thermal Shutdown Hysteresis
25
癈
Notes:
1. At turn-on, before the HSO load capacitor is charged, the current limit is set at the inrush level. After the capacitor has
been charged within ~1.25 V of VNEG, the operating current limit is engaged. This higher current limit remains active
until the UVLO lower limit has been tripped or until the hotswap switch is sufficiently current-limited to cause a foldback
of the HSO voltage.
2. Applies to non-isolated applications only (VOUT on schematic in Figure 1).
Table 6. Total Power Dissipation
Description
Condition
Min
Typ
Max
Units
Power Dissipation
VIN = 50 V, VOUT = 5 V, 2 A
0.7
W
Table 7. Package Thermal Characteristics
Parameter
Symbol
Test Condition
Typ
Units
Thermal resistance
(junction to ambient)
q
JA
Still air; assumes a minimum of
nine thermal vias are connected
to a 2 in
2
heat spreader plane for
the package pad node
(VNEG).
44
癈/W
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