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參數資料
| 型號： | SN74ALVC3651PCB |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2048 】 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY |
| 中文描述： | 2048】36 SYNCHRONOU仛先入先出存儲器 |
| 文件頁數： | 1/26頁 |
| 文件大小： | 383K |
| 代理商： | SN74ALVC3651PCB |
SN74ALVC3651
2048
×
36
SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY
SDMS025A – OCTOBER 1999 – REVISED DECEMBER 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
Clocked FIFO Buffering Data From Port A
to Port B
Synchronous Read-Retransmit Capability
Mailbox Register in Each Direction
Programmable Almost-Full (AF) and
Almost-Empty (AE) Flags
Microprocessor Interface Control Logic
Input-Ready and AF Flags Synchronized by
CLKA
Output-Ready and AE Flags Synchronized
by CLKB
Low-Power 0.8-
μ
m Advanced CMOS
Technology
Supports Clock Frequencies up to 100 MHz
Fast Access Times of 6.5 ns
Pin-to-Pin Compatible With 5-V Operating
SN74ACT3631, SN74ACT3641, and
SN74ACT3651
Package Options Include 120-Pin Thin
Quad Flat (PCB) and 132-Pin Plastic Quad
Flat (PQ) Packages
description
The SN74ALVC3651 is a high-speed, low-power, CMOS, synchronous FIFO memory that supports clock
frequencies up to 100 MHz and has read access times as fast as 6.5 ns. The 2048
×
36 dual-port SRAM FIFO
buffers data from port A to port B. The FIFO memory has retransmit capability, which allows previously read data
to be accessed again. The FIFO has flags to indicate empty and full conditions and two programmable flags
(almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication
between each port takes place with two 36-bit mailbox registers. Each mailbox register has a flag that signals
when new mail has been stored. Two or more devices are used in parallel to create wider data paths. Expansion
also is possible in word depth.
The SN74ALVC3651 is a synchronous FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple interface between microprocessors
and/or buses with synchronous control.
The input-ready (IR) flag and almost-full (AF) flag of the FIFO are two-stage, synchronized to CLKA. The
output-ready (OR) flag and almost-empty (AE) flag of the FIFO are two-stage, synchronized to CLKB. Offset
values for AF and AE are programmed from port A or through a serial input.
The SN74ALVC3651 is characterized for operation from 0
°
C to 70
°
C.
For more information on this device family, see the following application reports:
FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering
(literature number SCAA009)
FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control
(literature number SCAA007)
Metastability Performance of Clocked FIFOs(literature number SCZA004)
FIFO Architecture, Functions, and Applications(literature number SCAA042)
Optimizing DSP-Based Digital Filters With Application-Specific FIFOs(literature number SCAA021)
FIFO Memories: Surface-Mount Packages for PCMCIA Applications(literature number SDMA001A)
Interfacing TI Clocked FIFOs with TI Floating-Point DSPs(literature number SCAA005A)
Copyright
1999, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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PDF描述 |
|---|---|
| SN74ALVC3651PQ | 2048 】 36 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY |
| SN74ALVC7803DL | 512 】 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY |
| SN74ALVC7804DL | 512 】 18 FIRST-IN, FIRST-OUT MEMORY |
| SN74ALVC7805DL | 256 】 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY |
| SN74ALVC7806DL | 256 】 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SN74ALVC7803-20DL | 功能描述:先進先出 3.3V ABT 16-Bit Buff/Drv W/3-St Otpt RoHS:否 制造商:IDT 電路數量: 數據總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ALVC7803-20DLR | 功能描述:先進先出 512 x 18 3.3-V Synch 先進先出 Memory RoHS:否 制造商:IDT 電路數量: 數據總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ALVC7803-25DL | 功能描述:先進先出 16-Bit Buffer/Driver With 3-State Outputs RoHS:否 制造商:IDT 電路數量: 數據總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ALVC7803-25DLR | 功能描述:先進先出 512 x 18 3.3-V Synch 先進先出 Memory RoHS:否 制造商:IDT 電路數量: 數據總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
| SN74ALVC7803-40DL | 功能描述:先進先出 16-Bit Bus Trnscvr With 3-State Outputs RoHS:否 制造商:IDT 電路數量: 數據總線寬度:18 bit 總線定向:Unidirectional 存儲容量:4 Mbit 定時類型:Synchronous 組織:256 K x 18 最大時鐘頻率:100 MHz 訪問時間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝: |
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