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參數資料
| 型號： | SN74GTL1655DGGRE4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發器 |
| 英文描述： | GTL/TVC SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO64 |
| 封裝： | GREEN, PLASTIC, TSSOP-64 |
| 文件頁數： | 1/17頁 |
| 文件大小： | 336K |
| 代理商： | SN74GTL1655DGGRE4 |
www.ti.com
FEATURES
DESCRIPTION/ORDERING INFORMATION
DGG PACKAGE
(TOP VIEW)
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1OEAB
1OEBA
VCC
1A1
GND
1A2
1A3
GND
1A4
GND
1A5
GND
1A6
1A7
VCC
1A8
2A1
GND
2A2
2A3
GND
2A4
2A5
GND
2A6
GND
2A7
VCC
2A8
GND
2OEAB
2OEBA
CLK
1LEAB
1LEBA
VERC
GND
1B1
1B2
GND
1B3
1B4
1B5
GND
1B6
1B7
VCC
1B8
2B1
GND
2B2
2B3
GND
2B4
2B5
VREF
2B6
GND
2B7
2B8
BIAS VCC
2LEAB
2LEBA
OE
The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred
SN74GTL1655
16-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH LIVE INSERTION
SCBS696I – JULY 1997 – REVISED APRIL 2005
Member of the Texas Instruments Widebus
Family
UBT Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, or Clocked Modes
OEC Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
Translates Between GTL/GTL+ Signal Level
and LVTTL Logic Levels
High-Drive (100 mA), Low-Output-Impedance
(12
) Bus Transceiver (B Port)
Edge-Rate-Control Input Configures the
B-Port Output Rise and Fall Times
Ioff, Power-Up 3-State, and BIAS VCC Support
Live Insertion
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors on A
Port
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
The
SN74GTL1655
is
a
high-drive
(100
mA),
low-output-impedance
(12
)
16-bit
UBT
transceiver that provides LVTTL-to-GTL/GTL+ and
GTL/GTL+-to-LVTTL
signal-level
translation.
This
device is partitioned as two 8-bit transceivers and
combines D-type flip-flops and D-type latches to allow
for transparent, latched, and clocked modes of data
transfer similar to the '16501 function. This device
provides an interface between cards operating at
LVTTL logic levels and a backplane operating at
GTL/GTL+ signal levels. Higher-speed operation is a
direct result of the reduced output swing (<1 V),
reduced input threshold levels, and OEC circuitry.
The
high
drive
is
suitable
for
driving
double-terminated low-impedance backplanes using
incident-wave switching.
higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative
of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels, but are not 5-V
tolerant. VREF is the reference input voltage for the B port.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 1997–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SN74GTL1655DGGRG4 | 功能描述:轉換 - 電壓電平 16-Bit LVTTL To GTL/ GTL+ Univ Bus Trncvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
| SN74GTL16612ADGGR | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:BUS XCVR SGL 18CH 3-ST 56TSSOP - Tape and Reel |
| SN74GTL16612ADL | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74GTL16612ADLR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN74GTL16612DGGR | 功能描述:轉換 - 電壓電平 18Bit LVTTL/GTL/GTL+ Univ Bus Xcvr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MLF-8 |
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