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參數資料
型號: TFP401APZPG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, HTQFP-100
文件頁數: 15/20頁
文件大小: 295K
代理商: TFP401APZPG4
TFP401, TFP401A
TI
PanelBus DIGITAL RECEIVER
SLDS120C - MARCH 2000 REVISED MAY 2011
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
OGND
19,28,45,
58,76
GND
Output driver ground – Ground reference and current return for digital output drivers
OCK_INV
100
DI
ODCK Polarity – Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals
(HSYNC, VSYNC, DE, CTL1-3 ) are latched
Normal Mode:
High : Latches output data on rising ODCK edge
Low : Latches output data on falling ODCK edge
PD
2
DI
Power down – An active low signal that controls the TFP401/401A power-down state. During power down all
output buffers are switched to a high impedance state. All analog circuits are powered down and all inputs are
disabled, except for PD.
If PD is left unconnected an internal pullup will default the TFP401/401A to normal operation.
High : Normal operation
Low: Power down
PDO
9
DI
Output drive power down – An active low signal that controls the power-down state of the output drivers.
During output drive power down, the output drivers (except SCDT and CTL1) are driven to a high impedance
state. When PDO is left unconnected, an internal pullup defaults the TFP401/401A to normal operation.
High : Normal operation/output drivers on
Low: Output drive power down.
PGND
98
GND
PLL GND – Ground reference and current return for internal PLL
PIXS
4
DI
Pixel select – Selects between one or two pixels per clock output modes. During the 2-pixel/clock mode, both
even pixels, QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During
1-pixel/clock, even and odd pixels are output sequentially, one at a time, with the even pixel first, on the even
pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the
odd pixel.)
High : 2-pixel/clock
Low: 1-pixel/clock
PVDD
97
VDD
PLL VDD – Power supply for internal PLL
QE[8:15]
20-27
DO
Even green pixel output – Output for even and odd green pixels when in 1-pixel/clock mode. Output for even
only green pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE8/pin 20
MSB: QE15/pin 27
QE[16:23]
30-37
DO
Even red pixel output – Output for even and odd red pixels when in 1-pixel/clock mode. Output for even only
red pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE16/pin 30
MSB: QE23/pin 37
QO[0:7]
49-56
DO
Odd blue pixel output – Output for odd only blue pixel when in 2-pixel/clock mode. Not used, and held low,
when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO0/pin 49
MSB: QO7/pin 56
QO[8:15]
59-66
DO
Odd green pixel output – Output for odd only green pixel when in 2-pixel/clock mode. Not used, and held low,
when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO8/pin 59
MSB: QO15/pin 66
QO[16:23]
69-75,77
DO
Odd red pixel output – Output for odd only red pixel when in 2-pixel/clock mode. Not used, and held low, when
in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO16/pin 69
MSB: QO23/pin 77
QE[0:7]
10-17
DO
Even blue pixel output – Output for even and odd blue pixels when in 1-pixel/clock mode. Output for even only
blue pixel when in 2-pixel per clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE0/pin 10
MSB: QE7/pin 17
相關PDF資料
PDF描述
TFP401PZP SPECIALTY CONSUMER CIRCUIT, PQFP100
TFP401PZPG4 SPECIALTY CONSUMER CIRCUIT, PQFP100
TFP403PZP SPECIALTY CONSUMER CIRCUIT, PQFP100
TFP403PZPG4 SPECIALTY CONSUMER CIRCUIT, PQFP100
TFP420PAP SPECIALTY CONSUMER CIRCUIT, PQFP64
相關代理商/技術參數
參數描述
TFP401PZP 功能描述:顯示接口集成電路 PanelBus DVI Receiver 165MHz RoHS:否 制造商:Texas Instruments 電源電流:125 mA 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:WQFN-60 封裝:Reel
TFP401PZPG4 功能描述:顯示接口集成電路 PanelBus DVI Rcvr RoHS:否 制造商:Texas Instruments 電源電流:125 mA 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:WQFN-60 封裝:Reel
TFP403 制造商:TI 制造商全稱:Texas Instruments 功能描述:TI PANEBUS DIGITAL RECEIVER
TFP403PZP 功能描述:顯示接口集成電路 PanelBus DVI Receiver RoHS:否 制造商:Texas Instruments 電源電流:125 mA 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:WQFN-60 封裝:Reel
TFP403PZPG4 功能描述:顯示接口集成電路 PanelBus DVI Rcvr RoHS:否 制造商:Texas Instruments 電源電流:125 mA 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:WQFN-60 封裝:Reel
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