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參數(shù)資料
| 型號： | TFP513PAPG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1.00 MM HEIGHT, 0.50 MM PITCH, HTQFP-64 |
| 文件頁數(shù)： | 17/32頁 |
| 文件大小： | 1206K |
| 代理商： | TFP513PAPG4 |
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TFP513
TI PanelBus DIGITAL TRANSMITTER
SLLS611 AUGUST 2004
24
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
I2C interface (continued)
Following a start condition, each I2C device decodes the slave address. The TFP513 responds with an
acknowledge by pulling the SDA line low during the ninth clock cycle if it decodes the address as its address.
During subsequent subaddress and data cycles, the TFP513 responds with acknowledge as shown in
Figure 12. The subaddress is auto-incremented after each data cycle.
The transmitting device must not drive the SDA signal during the acknowledge cycle so that the receiving device
may drive the SDA signal low. The master indicates a not acknowledge condition (/A) by keeping the SDA signal
high just before it asserts the stop condition (P). This sequence terminates a read cycle as shown in Figure 13.
In order to minimize the number of bits that must be transferred for the HDCP link integrity check, a second read
format is supported. This access, shown in Figure 14, has an implicit subaddress equal to the starting location
for the HDCP receiver link verification response (R i).
The slave address consists of 7 bits of address along with 1 bit of read/write information (that is, read = 1 and
write = 0) as shown in Figure 12 through Figure 14. For the TFP513 the slave addresses are 0x70 for write
cycles and 0x71 for read cycles.
S
Slave Address
W
A
Subaddress
A
Data
A
Data
A
P
From Master
A Acknowledge
From Slave
S Start condition
P Stop Condition
R Read Condition = 1
W Write Condition = 0
Figure 12. I2C Write Cycle
S
Slave Address
W
A
Subaddress
A
Sr
Slave Address
R
A
Data
A
Data
/A
P
From Master
A Acknowledge
From Slave
S Start condition
/A Not acknowledge (SDA high)
P Stop Condition
R Read Condition = 1
Sr Restart Condition
W Write Condition = 0
Figure 13. I2C Read Cycle
S
Slave Address
R
A
Data
A
Data
/A
P
From Master
A Acknowledge
From Slave
S Start condition
/A Not acknowledge (SDA high)
P Stop Condition
R Read Condition = 1
Figure 14. HDCP Port Link Integrity Message Read
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