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參數資料
型號: THS1206QDAR
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝: PLASTIC, TSSOP-32
文件頁數: 24/43頁
文件大?。?/td> 722K
代理商: THS1206QDAR
THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
www.ti.com
30
TIMING AND SIGNAL DESCRIPTION OF THE THS1206
Read Timing (using R/W, CS0-controlled)
Figure 36 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W.
The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last
external signal of CS0, CS1, and R/W, which becomes valid.
90%
10%
tw(CS)
tsu(R/W)
th(R/W)
ta
th
td(CSDAV)
CS0
CS1
R/W
RD
D(0–11)
DATA_AV
Figure 36. Read Timing Diagram Using RD (CS0-controlled)
Read Timing Parameter (CS0-controlled)
PARAMETER
MIN
TYP
MAX
UNIT
tsu(R/W)
Setup time, R/W high to last CS valid
0
ns
ta
Access time, last CS valid to data valid
0
10
ns
td(CSDAV) Delay time, last CS valid to DATA_AV inactive
12
ns
th
Hold time, first CS invalid to data invalid
0
5
ns
th(R/W)
Hold time, first external CS invalid to R/W change
5
ns
tw(CS)
Pulse duration, CS active
10
ns
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