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參數資料
型號: THS1206QDAR
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝: PLASTIC, TSSOP-32
文件頁數: 26/43頁
文件大?。?/td> 722K
代理商: THS1206QDAR
THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
www.ti.com
32
INTERFACING THE THS1206 TO THE TMS320C54X USING I/O STROBE
The following application circuit shows an interface of the THS1206 to the TMS320C54x. The read and write timings (using
R/W, CS0-controlled) shown before are valid for this specific interface.
CS0
CS1
R/W
DATA_AV
CONV_CLK
DATA
RD
DVDD
THS1206
TMS320C54x
I/O STRB
A15
R/W
INTX
BCLK
DATA
Read Timing (using RD, RD-controlled)
Figure 38 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input RD acts
as the read-input in this configuration. This timing is called RD-controlled because RD is the last external signal of CS0,
CS1, and RD, which becomes valid.
90%
10%
tw(RD)
tsu(CS)
th(CS)
ta
th
td(CSDAV)
CS0
CS1
WR
RD
D(0–11)
DATA_AV
10%
Figure 38. Read Timing Diagram Using RD (RD-controlled)
Read Timing Parameter (RD-controlled)
PARAMETER
MIN
TYP
MAX
UNIT
tsu(CS)
Setup time, RD low to last CS valid
0
ns
ta
Access time, last CS valid to data valid
0
10
ns
td(CSDAV) Delay time, last CS valid to DATA_AV inactive
12
ns
th
Hold time, first CS invalid to data invalid
0
5
ns
th(CS)
Hold time, RD change to first CS invalid
5
ns
tw(RD)
Pulse duration, RD active
10
ns
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相關代理商/技術參數
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