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參數(shù)資料
| 型號： | THS14F03IPFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | GREEN, PLASTIC, TQFP-48 |
| 文件頁數(shù)： | 21/24頁 |
| 文件大小： | 329K |
| 代理商： | THS14F03IPFBG4 |
THS14F01, THS14F03
14-BIT, 1 MSPS/ 3 MSPS, DSP COMPATIBLE, ANALOG-TO-DIGITAL CONVERTERS
WITH FIFO INTERNAL REFERENCE AND PGA
SLAS285 – JUNE 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
sample timing
The THS14F01/3 core is based on a pipeline architecture with a latency of 9.5 samples. The conversion results
are stored in the FIFO 9.5 clock cycles after the input signal was sampled.
S9
S10
S11
S12
CLK
Data
to FIFO
Analog
Input
C1
C2
C3
tw(CLK)
td
INT
Figure 1. Sample Timing
INT goes active if the programmed FIFO level is reached. INT is either low or high active depending on the
polarity bit (IP) within the control word. This signal is set synchronously to the CLK signal. It is reset by a read
access to the FIFO once the number of samples in the FIFO is below the programmed threshold level.
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